bsp_cfg.h

freescale i.mx31 BSP CE5.0全部源码

//------------------------------------------------------------------------------
//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
//  THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
//  BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
//  FREESCALE SEMICONDUCTOR, INC.
//
//------------------------------------------------------------------------------
//
//  File:  bsp_cfg.h
//
//  This file contains system constant specific for MX31 EVB board.
//
//------------------------------------------------------------------------------
#ifndef __BSP_CFG_H
#define __BSP_CFG_H

//------------------------------------------------------------------------------
//
//  Define:  BSP_DEVICE_PREFIX
//
//  Prefix used to generate device name for bootload/KITL
//
#define BSP_DEVICE_PREFIX       "MX31"                  // Device name prefix

//------------------------------------------------------------------------------
// Clock Configuration Settings
//------------------------------------------------------------------------------
#define BSP_MAX_CORE_CLK_FREQ   532000000       // AP Max CPU clock = 532 MHz
#define RESCHED_PERIOD          1               // Reschedule ms
#define BSP_EPIT_PRESCALAR      (4-1)           // Prescalar for system timer

//------------------------------------------------------------------------------
// SDHC clock gating configuration
//------------------------------------------------------------------------------
#define BSP_CLK_GATING_BETWEEN_CMDS_SDHC1   TRUE
#define BSP_CLK_GATING_BETWEEN_CMDS_SDHC2   TRUE
#define BSP_SDHC_SDMA_MIN_TRANSFER          256

//------------------------------------------------------------------------------
// SDMA Configuration
//------------------------------------------------------------------------------
#define BSP_SDMA_MC0PTR         IMAGE_SHARE_IRAM_SDMA_PA_START

#define BSP_SDMA_CHNPRI_AUDIO   (SDMA_CHNPRI_CHNPRI_HIGHEST)
#define BSP_SDMA_CHNPRI_ATA     (SDMA_CHNPRI_CHNPRI_HIGHEST-1)
#define BSP_SDMA_CHNPRI_CSPI    (SDMA_CHNPRI_CHNPRI_HIGHEST-2)
#define BSP_SDMA_CHNPRI_SDHC1   (SDMA_CHNPRI_CHNPRI_HIGHEST-3)
#define BSP_SDMA_CHNPRI_SDHC2   (SDMA_CHNPRI_CHNPRI_HIGHEST-3)
#define BSP_SDMA_CHNPRI_SERIAL  (SDMA_CHNPRI_CHNPRI_HIGHEST-4)

#define BSP_SDMA_SUPPORT_ATA    TRUE
#define BSP_SDMA_SUPPORT_SSI1   TRUE
#define BSP_SDMA_SUPPORT_SSI2   TRUE
#define BSP_SDMA_SUPPORT_SDHC1  TRUE
#define BSP_SDMA_SUPPORT_SDHC2  TRUE
#define BSP_SDMA_SUPPORT_CSPI1  FALSE
#define BSP_SDMA_SUPPORT_CSPI2  FALSE
#define BSP_SDMA_SUPPORT_CSPI3  FALSE
#define BSP_SDMA_SUPPORT_UART1  FALSE
#define BSP_SDMA_SUPPORT_UART2  FALSE
#define BSP_SDMA_SUPPORT_UART3  FALSE
#define BSP_SDMA_SUPPORT_UART4  FALSE
#define BSP_SDMA_SUPPORT_UART5  FALSE
#define BSP_SDMA_SUPPORT_FIRI   FALSE
#define BSP_SDMA_SUPPORT_SIM    FALSE
#define BSP_SDMA_SUPPORT_NANDFC FALSE

//------------------------------------------------------------------------------
// Audio Configuration
//------------------------------------------------------------------------------

// Set BSP_AUDIO_DMA_BUF_ADDR to static DMA buffer physical address.  Comment
// out these two definitions to force the audio DMA buffers to be dynamically
// allocated by the audio driver from external RAM.
// #define BSP_AUDIO_DMA_BUF_ADDR  IMAGE_SHARE_IRAM_AUDIO_PA_START
// #define BSP_AUDIO_DMA_BUF_SIZE  IMAGE_SHARE_IRAM_AUDIO_SIZE

//------------------------------------------------------------------------------
// Ethernet Board Configuration
//------------------------------------------------------------------------------
#define BSP_CS8900_IRQ          IRQ_RESERVED1

//------------------------------------------------------------------------------
// USB Board Configuration
//------------------------------------------------------------------------------
#define BSP_USB_IRQ             IRQ_RESERVED38

//------------------------------------------------------------------------------
// PBC Board Configuration
//------------------------------------------------------------------------------
#define BSP_PBC_IRQ             BSP_CS8900_IRQ
#ifdef VPMX31
#define BSP_PBC_GPIO_PORT       DDK_GPIO_PORT1
#define BSP_PBC_GPIO_PIN        2
#define BSP_PBC_GPIO_LEVEL      GPIO_ICR_LOW_LEVEL
#else
#define BSP_PBC_GPIO_PORT       DDK_GPIO_PORT1
#define BSP_PBC_GPIO_PIN        4
#define BSP_PBC_GPIO_LEVEL      GPIO_ICR_HIGH_LEVEL
#endif // VPMX31

#define BSP_CS8900_GPIO_PORT    DDK_GPIO_PORT1
#define BSP_CS8900_GPIO_PIN      1
#define BSP_CS8900_GPIO_LEVEL  GPIO_ICR_HIGH_LEVEL

//------------------------------------------------------------------------------
// PBC User Switch Definitions
//------------------------------------------------------------------------------
#define BSP_PBC_DSW_KITL        (1 << 0)    // SW3_8:  ON = ACTIVE, OFF = PASSIVE
#define BSP_PBC_DSW_L2          (1 << 1)    // SW3_7:  ON = L2 enabled, OFF = L2 disabled
#define BSP_PBC_DSW_AHB_CLK     (1 << 2)    // SW3_6:  ON = 133MHz, OFF = 66MHz
#define BSP_PBC_DSW_ARM_CLK     (1 << 3)    // SW3_5:  ON = 532MHz, OFF = 266MHz
#define BSP_PBC_DSW_ALT_CLK     (1 << 4)    // SW3_4:  ON = SW3[5:6] determine clocking
                                            //        OFF = Force alternate clocking


//------------------------------------------------------------------------------
// PMIC Board Configuration
//------------------------------------------------------------------------------
#define BSP_PMIC_IRQ            IRQ_RESERVED0
#define BSP_PMIC_CSPI_FREQ      4000000 // 4 MHz (limited by ADS signal quality)
#ifdef VPMX31
#define BSP_PMIC_CSPI_PORT      1
#define BSP_PMIC_IOMUX_PIN      DDK_IOMUX_PIN_GPIO1_5
#define BSP_PMIC_IOMUX_PAD      DDK_IOMUX_PAD_GPIO1_5
#define BSP_PMIC_GPIO_PORT      DDK_GPIO_PORT1
#define BSP_PMIC_GPIO_PIN       5
#else
#define BSP_PMIC_CSPI_PORT      2
#define BSP_PMIC_IOMUX_PIN      DDK_IOMUX_PIN_GPIO1_3
#define BSP_PMIC_IOMUX_PAD      DDK_IOMUX_PAD_GPIO1_3
#define BSP_PMIC_GPIO_PORT      DDK_GPIO_PORT1
#define BSP_PMIC_GPIO_PIN       3
#endif // VPMX31
#define BSP_PMIC_CPU_REGULATOR  SW1A
#define BSP_PMIC_NORMAL_VOLT    0x1C    // MC13783 code for 1.600V
#define BSP_PMIC_STANDBY_VOLT   0x4     // MC13783 code for 1.0V
#define BSP_PMIC_LOWSPEED_VOLT  0x12    // MC13783 code for 1.350V      
#define BSP_PMIC_LOWBUS_VOLT    0x0F    // MC13783 code for 1.275V

//------------------------------------------------------------------------------
// LCD Panel Configuration to support IOCTL_HAL_QUERY_DISPLAYSETTINGS
//------------------------------------------------------------------------------
#define BSP_PREF_DISPLAY_WIDTH  240
#define BSP_PREF_DISPLAY_HEIGHT 320
#define BSP_PREF_DISPLAY_BPP    16

//------------------------------------------------------------------------------
// UART Configuration 
//------------------------------------------------------------------------------
#define BSP_GPIO_PWR_EN_IRDA		4	 //MCU3_4												
#define BSP_GPIO_PWR_EN_GPS			5	 //MCU3_5												
#define BSP_GPIO_IRDA_MODE_SET		13	 //MCU2_13
#define BSP_GPIO_IRDA_RS232			2	 //MCU3_2
#define BSP_GPIO_GPS_RS232			3	 //MCU3_3
//------------------------------------------------------------------------------
// Debug OUTPUT
// DEBUG_PORT specifies which UART we use for debug serial port. It must be one
// of the following :
//     DBG_UART1
//     DBG_SC16C652_PORTA
//     DBG_SC16C652_PORTB
//------------------------------------------------------------------------------
#define DBG_UART1               1
#define DBG_SC16C652_PORTA      4
#define DBG_SC16C652_PORTB      5

//#define DEBUG_PORT          DBG_SC16C652_PORTA
#define DEBUG_PORT          DBG_UART1

//------------------------------------------------------------------------------
// I2C Port
// The I2C_PORT specifies the which I2C device will be used.  It must be
// one of the following :
//     CAM_I2C_PORT
//     USB_I2C_PORT
//------------------------------------------------------------------------------
#define CAM_I2C_PORT           L"I2C1:"
#define USB_I2C_PORT           L"I2C3:"

//------------------------------------------------------------------------------
// Boot configuration data storage
// BOOTCFG_STORAGE specifies what storage is used for storage boot configuration
// data.
// It must be one of the following :
//     BOOTCFG_STORAGE_NAND
//     BOOTCFG_STORAGE_EEPROM
//-----------------------------------------------------------------------------
#define BOOTCFG_STORAGE_NAND        0
#define BOOTCFG_STORAGE_EEPROM      1

//#define BOOTCFG_STORAGE             BOOTCFG_STORAGE_NAND
#define BOOTCFG_STORAGE             BOOTCFG_STORAGE_EEPROM

//------------------------------------------------------------------------------
#define SYSINTR_USBOTG          (SYSINTR_FIRMWARE+2)
#endif