sdc.c

freescale i.mx31 BSP CE5.0全部源码

    switch (currentPanel -> TYPE)
    {
        case IPU_PANEL_SHARP_TFT:
            OUTREG32(&g_pIPU->DI_DISP3_TIME_CONF,
                  //..write strobe end
                  CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_DOWN_WR, (m_PixelDivider / 8) - 1) |
                  //.. period
                  CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_PER_WR, m_PixelDivider));
            break;

        case IPU_PANEL_NEC_TFT:
            OUTREG32(&g_pIPU->DI_DISP3_TIME_CONF,
                  //.. period
                  CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_PER_WR, 5 << 4)|
                  //..write strobe start
                  CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_UP_WR, 0)|
                  //..write strobe end
                  CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_DOWN_WR, 3 << 2));
            break;

        case IPU_TV_NTSC:
        case IPU_TV_PAL:
            OUTREG32(&g_pIPU->DI_DISP3_TIME_CONF,
                  //.. period
                  CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_PER_WR, 5 << 4)|
                  //..write strobe start
                  CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_UP_WR, 0)|
                  //..write strobe end
                  CSP_BITFVAL( IPU_DI_DISP3_TIME_CONF_DISP3_IF_CLK_DOWN_WR, (2 << 2|2)));
            break;
    }

    //... DI_DISP_ACC_CC
    INSREG32BF(&g_pIPU->DI_DISP_ACC_CC,
                // display clock cycles number (data access)
                IPU_DI_DISP_ACC_CC_DISP3_IF_CLK_CNT_D, 0);


    //... DI_DISP3_B0_MAP
    OUTREG32(&g_pIPU->DI_DISP3_B0_MAP,
                // set0; data offset
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_OFFS0, 0x5)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_OFFS1, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_OFFS2, 0)|

                // set0; data maping
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M0, 3)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M1, 3)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M2, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M3, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M4, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M5, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M6, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B0_MAP_M30_M7, 0));



    //... DI_DISP3_B1_MAP
    OUTREG32(&g_pIPU->DI_DISP3_B1_MAP,
                // set1; data offset
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_OFFS0, 0xb)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_OFFS1, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_OFFS2, 0)|

                // set1; data maping
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M0, 3)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M1, 3)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M2, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M3, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M4, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M5, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M6, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B1_MAP_M31_M7, 0));


    //... DI_DISP3_B2_MAP
    OUTREG32(&g_pIPU->DI_DISP3_B2_MAP,
                // set2; data offset
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_OFFS0, 0x11)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_OFFS1, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_OFFS2, 0)|

                // set2; data maping
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M0, 3)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M1, 3)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M2, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M3, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M4, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M5, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M6, 0)|
                CSP_BITFVAL( IPU_DI_DISP3_B2_MAP_M32_M7, 0));


    //----- SDC Configuration
    INSREG32BF(&g_pIPU->SDC_COM_CONF,
                IPU_SDC_COM_CONF_GWSEL, IPU_SDC_COM_CONF_GWSEL_BG);
    INSREG32BF(&g_pIPU->SDC_COM_CONF,
                IPU_SDC_COM_CONF_SDC_GLB_LOC_A, 1);

#ifdef VPMX31
    OUTREG32(&g_pIPU->SDC_BG_POS,
                CSP_BITFVAL( IPU_SDC_BG_POS_BGXP, 0x0)|
                CSP_BITFVAL( IPU_SDC_BG_POS_BGYP, 0x0));

    OUTREG32(&g_pIPU->SDC_FG_POS,
                CSP_BITFVAL( IPU_SDC_FG_POS_FGXP, 0x0)|
                CSP_BITFVAL( IPU_SDC_FG_POS_FGYP, 0x0));
#else
    OUTREG32(&g_pIPU->SDC_BG_POS,
                CSP_BITFVAL( IPU_SDC_BG_POS_BGXP, currentPanel -> HSTARTWIDTH )|
                CSP_BITFVAL( IPU_SDC_BG_POS_BGYP, currentPanel -> VSTARTWIDTH ));

    OUTREG32(&g_pIPU->SDC_FG_POS,
                CSP_BITFVAL( IPU_SDC_FG_POS_FGXP, (currentPanel -> HSTARTWIDTH + 1) )|
                CSP_BITFVAL( IPU_SDC_FG_POS_FGYP, currentPanel -> VSTARTWIDTH ));
#endif


    //----- IDMAC Configuration

    // Set no double-buffer, use buf0
    INSREG32BF(&g_pIPU->IPU_CHA_DB_MODE_SEL, IPU_DMA_CHA_DMASDC_0, IPU_SIG_BUF);
    INSREG32BF(&g_pIPU->IPU_CHA_DB_MODE_SEL, IPU_DMA_CHA_DMASDC_1, IPU_SIG_BUF);


    // Set buffer 0 as current buffer (non double buffered)
    INSREG32BF(&g_pIPU->IPU_CHA_CUR_BUF, IPU_DMA_CHA_DMASDC_0, IPU_SIG_BUF);
    INSREG32BF(&g_pIPU->IPU_CHA_CUR_BUF, IPU_DMA_CHA_DMASDC_1, IPU_SIG_BUF);

    // Set high priority for DMA SDC Channel 0
    INSREG32BF(&g_pIPU->IDMAC_CHA_PRI,
                IPU_DMA_CHA_DMASDC_0, 1);

    // Set high priority for DMA SDC Channel 1
    INSREG32BF(&g_pIPU->IDMAC_CHA_PRI,
                IPU_DMA_CHA_DMASDC_1, 1);

    // Set max for consecutive bursts for each channel
    INSREG32BF(&g_pIPU->IDMAC_CONF,
                IPU_IDMAC_CONF_SRCNT, 7);

    // Select source of SDC channel as ARM
    OUTREG32(&g_pIPU->IPU_FS_DISP_FLOW,
                CSP_BITFVAL( IPU_IPU_FS_DISP_FLOW_SDC0_SRC_SEL, FLOW_ARM)|
                CSP_BITFVAL( IPU_IPU_FS_DISP_FLOW_SDC1_SRC_SEL, FLOW_ARM));

    // Turn contrast fully on
    OUTREG32(&g_pIPU->SDC_CUR_BLINK_PWM_CTRL,
                CSP_BITFVAL( IPU_SDC_CUR_BLINK_PWM_CTRL_SCR, 1)|
                CSP_BITFVAL( IPU_SDC_CUR_BLINK_PWM_CTRL_CC_EN, 1)|
                CSP_BITFVAL( IPU_SDC_CUR_BLINK_PWM_CTRL_PWM, 0x8F));

    _init_dma(currentPanel -> WIDTH, currentPanel -> HEIGHT, bpp, FALSE, SDC_DMA_CHANNEL);

    g_pCurrentPanel = currentPanel;

    ret = TRUE;
    return ret;
}


//------------------------------------------------------------------------------
//
// Function: EnableSDC
//
// This function enables SDC for normal opertion
//
// Parameters:
//      none
//
// Returns:
//      none.
//------------------------------------------------------------------------------
void EnableSDC(void)
{
    UINT32 iOldVal, iNewVal, iMask, iBitval;

    // Configure IOMUX to request IPU SDC pins
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD0, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD1, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD2, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD3, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD4, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD5, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD6, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD7, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD8, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD9, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD10, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD11, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD12, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD13, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD14, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD15, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD16, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD17, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_VSYNC3, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_HSYNC, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_FPSHIFT, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_DRDY0, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_D3_REV, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_CONTRAST, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_D3_SPL, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_D3_CLS, DDK_IOMUX_OUT_FUNC, DDK_IOMUX_IN_FUNC);

    // Enable DI and SDC

    // Compute bitmask and shifted bit value for IPU Conf register
    iMask = CSP_BITFMASK(IPU_IPU_CONF_DI_EN)
                | CSP_BITFMASK(IPU_IPU_CONF_SDC_EN);
    iBitval = CSP_BITFVAL( IPU_IPU_CONF_DI_EN, IPU_IPU_CONF_DI_EN_ENABLE)
                | CSP_BITFVAL( IPU_IPU_CONF_SDC_EN, IPU_IPU_CONF_SDC_EN_ENABLE);

    // Use interlocked function to Enable DI and SDC.
    do
    {
        iOldVal = INREG32(&g_pIPU->IPU_CONF);
        iNewVal = (iOldVal & (~iMask)) | iBitval;
    } while (InterlockedTestExchange(&g_pIPU->IPU_CONF,
                iOldVal, iNewVal) != iOldVal);


    // Enable DMA SDC Channel 1

    // Compute bitmask and shifted bit value for IPU Conf register
    iMask = CSP_BITFMASK(IPU_DMA_CHA_DMASDC_0);
    iBitval = CSP_BITFVAL(IPU_DMA_CHA_DMASDC_0, IPU_ENABLE);

    // Use interlocked function to Enable DMA SDC Channel 1.
    do
    {
        iOldVal = INREG32(&g_pIPU->IDMAC_CHA_EN);
        iNewVal = (iOldVal & (~iMask)) | iBitval;
    } while (InterlockedTestExchange(&g_pIPU->IDMAC_CHA_EN,
                iOldVal, iNewVal) != iOldVal);

    // Enable SDC background
    // Set BG_EN = 1 (Background is enabled)
    INSREG32BF(&g_pIPU->SDC_COM_CONF,
                IPU_SDC_COM_CONF_BG_EN, IPU_ENABLE);

    // Set DMA SDC Channel 0 as ready
    SETREG32(&g_pIPU->IPU_CHA_BUF0_RDY,
                CSP_BITFVAL(IPU_DMA_CHA_DMASDC_0, IPU_DMA_CHA_READY));

}


//------------------------------------------------------------------------------
//
// Function: DisableSDC
//
// This function disables SDC
//
// Parameters:
//      none
//
// Returns:
//      none.
//------------------------------------------------------------------------------
void DisableSDC(void)
{
    UINT32 uTempReg1, uTempReg2, uCount = 0;
    UINT32 oldVal, newVal, iMask, iBitval;


    // Compute bitmask and shifted bit value for SDC_COM_CONF reg.
    iMask = CSP_BITFMASK(IPU_SDC_COM_CONF_BG_EN);
    iBitval = CSP_BITFVAL(IPU_SDC_COM_CONF_BG_EN, IPU_DISABLE);

    // Use interlocked function to Disable SDC FG and BG.
    do
    {
        oldVal = INREG32(&g_pIPU->SDC_COM_CONF);
        newVal = (oldVal & (~iMask)) | iBitval;
    } while (InterlockedTestExchange(&g_pIPU->SDC_COM_CONF,
                oldVal, newVal) != oldVal);

    // Can we do this, or perhaps not because a system
    // level call is required (WaitForSingleObject)?
    // DisplayPlaneWaitForNotBusy(DisplayPlane_0);

    // initalize ... for the first time through
    uTempReg1 = INREG32(&g_pIPU->IDMAC_CHA_BUSY);
    uTempReg2 = INREG32(&g_pIPU->IPU_CHA_BUF0_RDY);

    // We can't disable tasks until the active channel
    // has completed its current frames.  Make sure
    // that buffers aren't set as ready (indicating that
    // they are yet to start) and that channels are
    // not busy (indicating that channels are still running).
    while ((uTempReg1 & (1 << GRAPHICS_DMA_CHANNEL)) || (uTempReg2 & (1 << GRAPHICS_DMA_CHANNEL)))
    {
        if (uCount <= DELAYTIMEOUT)
        {
            uCount++;

            //.. need to check after the sleep delay
            uTempReg1 = INREG32(&g_pIPU->IDMAC_CHA_BUSY);
            uTempReg2 = INREG32(&g_pIPU->IPU_CHA_BUF0_RDY);
        }
        else
        {
            //.. there is something wrong ....break out
            return;
        }
    }

    // Compute bitmask and shifted bit value for idmac register
    iMask = CSP_BITFMASK(IPU_DMA_CHA_DMASDC_0);
    iBitval = CSP_BITFVAL(IPU_DMA_CHA_DMASDC_0, IPU_DISABLE);

    // Use interlocked function to Disable DMA SDC Channel 0.
    do
    {
        oldVal = INREG32(&g_pIPU->IDMAC_CHA_EN);
        newVal = (oldVal & (~iMask)) | iBitval;
    } while (InterlockedTestExchange(&g_pIPU->IDMAC_CHA_EN,
                oldVal, newVal) != oldVal);


    // Compute bitmask and shifted bit value for IPU_CONF reg.
    iMask = CSP_BITFMASK(IPU_IPU_CONF_DI_EN)
            | CSP_BITFMASK(IPU_IPU_CONF_SDC_EN);
    iBitval = CSP_BITFVAL(IPU_IPU_CONF_DI_EN, IPU_IPU_CONF_DI_EN_DISABLE)
            | CSP_BITFVAL(IPU_IPU_CONF_SDC_EN, IPU_IPU_CONF_DI_EN_DISABLE);

    // Use interlocked function to Disable DI and SDC modules.
    do
    {
        oldVal = INREG32(&g_pIPU->IPU_CONF);
        newVal = (oldVal & (~iMask)) | iBitval;
    } while (InterlockedTestExchange(&g_pIPU->IPU_CONF,
                oldVal, newVal) != oldVal);

    // Configure IOMUX to release IPU SDC pins
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD0, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD1, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD2, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD3, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD4, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD5, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD6, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD7, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD8, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD9, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD10, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD11, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD12, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD13, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD14, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD15, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD16, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_LD17, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_VSYNC3, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_HSYNC, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_FPSHIFT, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_DRDY0, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_D3_REV, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_CONTRAST, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_D3_SPL, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
    DDKIomuxSetPinMux(DDK_IOMUX_PIN_D3_CLS, DDK_IOMUX_OUT_GPIO, DDK_IOMUX_IN_NONE);
}

//------------------------------------------------------------------------------
//
// Function: BackgroundSetSrcBuffer
//
// This function sets the source buffer for the main background display window.
//
// Parameters:
//      pAddr
//          [in] Address of buffer to set as source for main background
//              display window.
//
// Returns:
//      none.
//------------------------------------------------------------------------------
void BackgroundSetSrcBuffer(PHYSICAL_ADDRESS *pAddr)
{
    SetSrcBuffer(SDC_DMA_CHANNEL, pAddr, eBUF_0);
}

//------------------------------------------------------------------------------
//
// Function: _init_dma
//
// Init the IPU DMA module
//
// Parameters:
//      None.
//
// Returns: