adc_init.c

freescale i.mx31 BSP CE5.0全部源码

        break;
    case RGB_444_FORMAT:
        ColorMode = 0x38;
        break;
    }

    StartPage[0] = SPage & 0xFF;
    StartPage[1] = (SPage & 0xFF00) >> 8;
    EndPage[0] = EPage & 0xFF;
    EndPage[1] = (EPage & 0xFF00) >> 8;
    StartCol[0] = SCol & 0xFF;
    StartCol[1] = (SCol & 0xFF00) >> 8;
    EndCol[0] = ECol & 0xFF;
    EndCol[1] = (ECol & 0xFF00) >> 8;

    pCmd[i].reg.Data = CMD_DATCTL;
    pCmd[i].reg.Opcode = WR_CMND;
    pCmd[i++].reg.FlowControl = SINGLE_STEP;
    pCmd[i].reg.Data = ColorMode;
    pCmd[i].reg.Opcode = WR_CMND;
    pCmd[i++].reg.FlowControl = SINGLE_STEP;

    pCmd[i].reg.Data = CMD_SD_PSET;          //Page
    pCmd[i].reg.Opcode = WR_CMND;
    pCmd[i++].reg.FlowControl = SINGLE_STEP;
    pCmd[i].reg.Data = StartPage[0];         //Start
    pCmd[i].reg.Opcode = WR_CMND;
    pCmd[i++].reg.FlowControl = SINGLE_STEP;
    pCmd[i].reg.Data = StartPage[1];
    pCmd[i].reg.Opcode = WR_CMND;
    pCmd[i++].reg.FlowControl = SINGLE_STEP;
    pCmd[i].reg.Data = EndPage[0];           //End
    pCmd[i].reg.Opcode = WR_CMND;
    pCmd[i++].reg.FlowControl = SINGLE_STEP;
    pCmd[i].reg.Data = EndPage[1];
    pCmd[i].reg.Opcode = WR_CMND;
    pCmd[i++].reg.FlowControl = SINGLE_STEP;

    pCmd[i].reg.Data = CMD_SD_CSET;          //Column
    pCmd[i].reg.Opcode = WR_CMND;
    pCmd[i++].reg.FlowControl = SINGLE_STEP;
    pCmd[i].reg.Data = StartCol[0];          //Start
    pCmd[i].reg.Opcode = WR_CMND;
    pCmd[i++].reg.FlowControl = SINGLE_STEP;
    pCmd[i].reg.Data = StartCol[1];
    pCmd[i].reg.Opcode = WR_CMND;
    pCmd[i++].reg.FlowControl = SINGLE_STEP;
    pCmd[i].reg.Data = EndCol[0];            //End
    pCmd[i].reg.Opcode = WR_CMND;
    pCmd[i++].reg.FlowControl = SINGLE_STEP;
    pCmd[i].reg.Data = EndCol[1];
    pCmd[i].reg.Opcode = WR_CMND;
    pCmd[i++].reg.FlowControl = SINGLE_STEP;

    // SLPOUT and DISON should not be needed once Virtio supports
    // low level access.

    pCmd[i].reg.Data = CMD_SLPOUT;           //Sleep Out
    pCmd[i].reg.Opcode = WR_CMND;
    pCmd[i++].reg.FlowControl = SINGLE_STEP;

    pCmd[i].reg.Data = CMD_DISON;            //Display On
    pCmd[i].reg.Opcode = WR_CMND;
    pCmd[i++].reg.FlowControl = SINGLE_STEP;

    if (Write)
    {
        pCmd[i].reg.Data = CMD_RAMWR;        //RAM Wr
        pCmd[i].reg.Opcode = WR_CMND;
        pCmd[i++].reg.FlowControl = SINGLE_STEP;

        pCmd[i].reg.Data = 0x0;              //Write data
        pCmd[i].reg.Opcode = WR_DATA;
        pCmd[i++].reg.FlowControl = STOP;
    }
    else
    {
        pCmd[i].reg.Data = CMD_RAMRD;        //RAM RD
        pCmd[i].reg.Opcode = WR_CMND;
        pCmd[i++].reg.FlowControl = SINGLE_STEP;

        pCmd[i].reg.Data = 0x0;              //Read data
        pCmd[i].reg.Opcode = RD_DATA;
        pCmd[i++].reg.FlowControl = STOP;
    }

}

//Program the template memory
void _program_template(TEMPLATE_CMD_REG * pCmd, unsigned int Display, BOOL Write)
{
    unsigned int ima_addr;
    unsigned int row_nu;
    int i;


    // Set IPU_IMA_ADDR (IPU Internal Memory Access Address)
    // MEM_NU = 0x0001 (CPM)
    // ROW_NU = 2*N ( N is channel number)
    // WORD_NU = 0
    if (Write)
    {
        row_nu = Display * 2 * ATM_ADDR_RANGE;
    }
    else
    {
        row_nu = (Display * 2 + 1) * ATM_ADDR_RANGE;
    }

    ima_addr = CSP_BITFVAL(IPU_IPU_IMA_ADDR_MEM_NU, IPU_IMA_ADDR_MEM_NU_TM) |
               CSP_BITFVAL(IPU_IPU_IMA_ADDR_ROW_NU, row_nu) |
               CSP_BITFVAL(IPU_IPU_IMA_ADDR_WORD_NU, 0);

    OUTREG32(&g_pIPU->IPU_IMA_ADDR, ima_addr);

    for (i = 0; i < TEMPLATE_BUF_SIZE; i++)
    {
        OUTREG32(&g_pIPU->IPU_IMA_DATA, pCmd[i].data);
    }
}


//Setup the specified channel
void _setup_channel(BOOL Enabled, unsigned int Display, unsigned int StartAddr,
                  unsigned int Ch, unsigned int Mode, BOOL Write, BOOL b24Bit)
{
    UINT32 Conf = 0;
    unsigned char addr_inc;


    if ( 1 == b24Bit)
    {
        addr_inc = IPU_ADC_ADDR_INC_4;
    }
    else
    {
        addr_inc = IPU_ADC_ADDR_INC_1;
    }

    switch (Ch)
    {
    case CHANNEL_SYS1:
        if (0 == Mode)
        {
            INSREG32BF(&Conf, IPU_ADC_CONF_SYS1_MODE, 0x7); //Cmd buffer mode
        }
        else if ((1 == Mode) && (1 == Write))
        {
            INSREG32BF(&Conf, IPU_ADC_CONF_SYS1_MODE, 0x1); //Template write
        }
        else
        {
            INSREG32BF(&Conf, IPU_ADC_CONF_SYS1_MODE, 0x2); //Template read
        }

        INSREG32BF(&Conf, IPU_ADC_CONF_SYS1_DISP_NUM, Display);
        INSREG32BF(&Conf, IPU_ADC_CONF_SYS1_ADDR_INC, addr_inc);
        INSREG32BF(&Conf, IPU_ADC_CONF_SYS1_DATA_MAP, 0);
        break;

    case CHANNEL_SYS2:
        if (0 == Mode)
        {
            INSREG32BF(&Conf, IPU_ADC_CONF_SYS2_MODE, 0x7); //Cmd buffer mode
        }
        else if ((1 == Mode) && (1 == Write))
        {
            INSREG32BF(&Conf, IPU_ADC_CONF_SYS2_MODE, 0x1); //Template write
        }
        else
        {
            INSREG32BF(&Conf, IPU_ADC_CONF_SYS2_MODE, 0x2); //Template read
        }

        INSREG32BF(&Conf, IPU_ADC_CONF_SYS2_DISP_NUM, Display);
        INSREG32BF(&Conf, IPU_ADC_CONF_SYS2_ADDR_INC, addr_inc);
        INSREG32BF(&Conf, IPU_ADC_CONF_SYS2_DATA_MAP, 0);
        break;

    case CHANNEL_PRP:
        INSREG32BF(&Conf, IPU_ADC_CONF_PRP_CHAN_EN, IPU_ENABLE);
        INSREG32BF(&Conf, IPU_ADC_CONF_PRP_DISP_NUM, Display);
        INSREG32BF(&Conf, IPU_ADC_CONF_PRP_ADDR_INC, addr_inc);
        INSREG32BF(&Conf, IPU_ADC_CONF_PRP_DATA_MAP, 0);
        break;

    case CHANNEL_PP:
        INSREG32BF(&Conf, IPU_ADC_CONF_PP_CHAN_EN, IPU_ENABLE);
        INSREG32BF(&Conf, IPU_ADC_CONF_PP_DISP_NUM, Display);
        INSREG32BF(&Conf, IPU_ADC_CONF_PP_ADDR_INC, addr_inc);
        INSREG32BF(&Conf, IPU_ADC_CONF_PP_DATA_MAP, 0);
        break;
    }

    OUTREG32(&g_pIPU->ADC_CONF, Conf);

    INSREG32BF(&g_pIPU->ADC_SYSCHA1_SA, IPU_ADC_CHA_CHAN_SA, StartAddr);
}

void _setup_display(unsigned int display, unsigned int sl,
                    unsigned int disp_type, unsigned int data_width,
                    unsigned int data_map)
{
    UINT32 conf = 0;

    INSREG32BF(&conf, IPU_ADC_DISP_CONF_DISP_SL, sl);
    INSREG32BF(&conf, IPU_ADC_DISP_CONF_DISP_TYPE, disp_type);
    INSREG32BF(&conf, IPU_ADC_DISP_CONF_DISP_DATA_WIDTH, data_width);
    INSREG32BF(&conf, IPU_ADC_DISP_CONF_DISP_DATA_MAP, data_map);

    switch (display)
    {
    case IPU_ADC_DISPLAY_0:
        OUTREG32(&g_pIPU->ADC_DISP0_CONF, conf);
        break;

    case IPU_ADC_DISPLAY_1:
        OUTREG32(&g_pIPU->ADC_DISP1_CONF, conf);
        break;

    case IPU_ADC_DISPLAY_2:
        OUTREG32(&g_pIPU->ADC_DISP2_CONF, conf);
        break;
    }
}

//------------------------------------------------------------------------------
//
// Function: _init_adc_dma
//
// Init the IPU DMA module for SDC operations.
//
// Parameters:
//      None.
//
// Returns:
//      None.
//------------------------------------------------------------------------------
static void _init_adc_dma(int width, int height, int bpp)
{
    UINT32 ima_addr = 0;
    UINT32 bpp_code;

    //
    // Configure First 132 bit word
    //

    // Set IPU IPU_IMA_ADDR (IPU Internal Memory Access Address)
    // MEM_NU = 0x0001 (CPM)
    // ROW_NU = 2*N + 1 (N is channel number)
    // WORD_NU = 0
    ima_addr = CSP_BITFVAL(IPU_IPU_IMA_ADDR_MEM_NU, IPU_IMA_ADDR_MEM_NU_CPM) |
               CSP_BITFVAL(IPU_IPU_IMA_ADDR_ROW_NU, (2 * IPU_DMA_CHA_DMAADC_2_LSH)) |
               CSP_BITFVAL(IPU_IPU_IMA_ADDR_WORD_NU, 0);

    OUTREG32(&g_pIPU->IPU_IMA_ADDR, ima_addr);

    // word 0
    // XV [9:0], YV [19:10], XB [31:20]
    OUTREG32(&g_pIPU->IPU_IMA_DATA, 0);

    // word 1
    // YB [11:0], SCE [12], RESERVED [13], NSB [14], LNPB [20:15], SX [30:21],
    // SY~ [31]
    // - Set NSB
    OUTREG32(&g_pIPU->IPU_IMA_DATA, (1 << 14));

    // word 2
    // ~SY [8:0], NS [18:9], SM [28:10] SDX~ [31:29]
    OUTREG32(&g_pIPU->IPU_IMA_DATA, 0);

    // word 3
    // ~SDX [1:0], SDY [6:2], SDRX [7], SDRY [8], SCRQ [9], RESERVED [11:10]
    // - FW [23:12], FH~ [31:24]
    // - Set FW & FH
    OUTREG32(&g_pIPU->IPU_IMA_DATA,
             (((width - 1) << 12) | ((height - 1) << 24)));

    // word 4
    // ~FH [3:0]
    OUTREG32(&g_pIPU->IPU_IMA_DATA, ((height - 1) >> 8));


    //
    // Configure Second 132 bit word
    //

    // Set IPU IPU_IMA_ADDR (IPU Internal Memory Access Address)
    // MEM_NU = 0x0001 (CPM)
    // ROW_NU = 2*N + 1 (N is channel number)
    // WORD_NU = 0
    ima_addr = CSP_BITFVAL(IPU_IPU_IMA_ADDR_MEM_NU, IPU_IMA_ADDR_MEM_NU_CPM) |
               CSP_BITFVAL(IPU_IPU_IMA_ADDR_ROW_NU, (2 * IPU_DMA_CHA_DMAADC_2_LSH + 1)) |
               CSP_BITFVAL(IPU_IPU_IMA_ADDR_WORD_NU, 0);

    // word 0
    // EBA0 [31:0]
    // Set buffer #0 to physical frame buffer address
    OUTREG32(&g_pIPU->IPU_IMA_DATA, BSP_BASE_REG_PA_FRAMEBUFFER);

    // word 1
    // EBA1 [31:0]
    OUTREG32(&g_pIPU->IPU_IMA_DATA, 0);

    // word 2
    // BPP [2:0], SL [16:3], PFS [19:17], BAM [24:20], NPB [30:25],
    // RESERVED [31]
    // - Set BPP
    // - Set SL (Scaling Factor) to (width * bpp / 8)
    // - Set PFS (Packing) to RGB (%100)
    switch (bpp) {
    case 32:
        bpp_code = 0;
        break;

    case 24:
        bpp_code = 1;
        break;

    case 16:
        bpp_code = 2;
        break;

    case 8:
        bpp_code = 3;
        break;

    case 4:
        bpp_code = 4;
        break;

    case 1:
        bpp_code = 5;
        break;

    default:
        bpp_code = 7;
        break;
    }

    OUTREG32(&g_pIPU->IPU_IMA_DATA,
             (bpp_code | (((width * bpp / 8) - 1) << 3) | (4 << 17)));

    // word 3
    // SAT [1:0], SCC [2], OFS0 [7:3], 0FS1 [12:8], OFS2 [17:13], OFS3 [22:18]
    // - WID0 [25:23], WID1 [28:26], WID2 [31:29]
    // Set OFS1 (8 - 8 bit shift), Color component 1 offset (Green)
    // Set OFS2 (16 - 16 bit shift), Color component 2 offset (Blue)
    // Set OFS3 (24 - 24 bit shift), Color component 3 offset (Alpha)
    // Set WID0 (7 - 8 bit size), Color component 0 width (Red)
    // Set WID1 (7 - 8 bit size), Color component 1 width (Green)
    // Set WID2 (7 - 8 bit size), Color component 2 width (Blue)
    if (bpp == 16)
    {
        OUTREG32(&g_pIPU->IPU_IMA_DATA,
                 ((5 << 8) |
                  (11 << 13) |
                  (24 << 18) |
                  (4 << 23) |
                  (5 << 26) |
                  (4 << 29)));
    }
    else  // 24 bpp as default
    {
        OUTREG32(&g_pIPU->IPU_IMA_DATA,
                 ((8 << 8) |
                  (16 << 13) |
                  (24 << 18) |
                  (7 << 23) |
                  (7 << 26) |
                  (7 << 29)));
    }

    // word 4
    // WID3 [2:0], DEC_SEL [3],
    // Set WID3 (7 - 8 bit size), Color component 3 width (Alpha)
    OUTREG32(&g_pIPU->IPU_IMA_DATA, 7);

}