📄 fs453.cpp
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CSP_BITFVAL(FS453_PWR_MGNT_PLL_PD, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_CLKOFF, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_CLK_SOFF, FS453_PWR_MGNT_CLK_SOFF_HDTV_CLK_OFF) | //SDTV Clock On
CSP_BITFVAL(FS453_PWR_MGNT_DAC_D_LP, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_C_LP, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_B_LP, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_A_LP, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_BGAP_OFF, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_D_OFF, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_C_OFF, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_B_OFF, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_A_OFF, FS453_SET_DISABLE) );
rc = Fs453WriteRegister(FS453_PWR_MGNT, &data); //0x200
// ... Issue a SRESET
m_fs453SwReset();
// ------------------------------------------------------------------------
// ------ Set scale and position factors
// ... position
data = CSP_BITFVAL(FS453_IHO_IHO, pFs453Param[FS453_PARAM_POSITION_HORIZ]);
Fs453WriteRegister(FS453_IHO, &data); //0x40
data = CSP_BITFVAL(FS453_IVO_IVO, pFs453Param[FS453_PARAM_POSITION_VERTI]);
Fs453WriteRegister(FS453_IVO, &data); //0x18
data = CSP_BITFVAL(FS453_IHW_IHW, pFs453Param[FS453_PARAM_HACTIVE]);
Fs453WriteRegister(FS453_IHW, &data); //0x280
// ... scale
data = CSP_BITFVAL(FS453_VSC_VSC, pFs453Param[FS453_PARAM_SCALE_VERTI]);
Fs453WriteRegister(FS453_VSC, &data); //0x276
data = (CSP_BITFVAL(FS453_HSC_HUSC, pFs453Param[FS453_PARAM_SCALE_HORIZ_UPSCALE])|
CSP_BITFVAL(FS453_HSC_HDSC, pFs453Param[FS453_PARAM_SCALE_HORIZ_DOWNSCALE]));
Fs453WriteRegister(FS453_HSC, &data); //0x1000
// ...
data = (CSP_BITFVAL(FS453_BYPASS_CAC_BYPASS, FS453_SET_ENABLE)|
CSP_BITFVAL(FS453_BYPASS_HDS_BYPASS, FS453_SET_ENABLE));
Fs453WriteRegister(FS453_BYPASS, &data); //0x000A for NTSC - not using horizon down scale
data = CSP_BITFVAL(FS453_FIFO_LAT_FIFO_LAT, pFs453Param[FS453_PARAM_FIFO_LATENCY]);
Fs453WriteRegister(FS453_FIFO_LAT, &data); //0x00a4 for NTSC
// ------------------------------------------------------------------------
// ------ Set PLL Register
// ... Set NCONL
data = CSP_BITFVAL(FS453_NCONL_NCONL, pFs453Param[FS453_PARAM_PLL_NCONL]);
Fs453WriteRegister(FS453_NCONL, &data); //0x0000
// ... Set NCONH
data = CSP_BITFVAL(FS453_NCONH_NCONH, pFs453Param[FS453_PARAM_PLL_NCONH]);
Fs453WriteRegister(FS453_NCONH, &data); //0x0000
// ... Set NCODL
data = CSP_BITFVAL(FS453_NCODL_NCODL, pFs453Param[FS453_PARAM_PLL_NCODL]);
Fs453WriteRegister(FS453_NCODL, &data); //0x0000
// ... Set NCODH
data = CSP_BITFVAL(FS453_NCODH_NCODH, pFs453Param[FS453_PARAM_PLL_NCODH]);
Fs453WriteRegister(FS453_NCODH, &data); //0x0000
// ... Set PLLM
data = CSP_BITFVAL(FS453_PLLM_PUMPCNTL_PLLM, pFs453Param[FS453_PARAM_PLL_M]);
Fs453WriteRegister(FS453_PLLM_PUMPCNTL, &data); //0x30f7
// ... Set PLLN
data = CSP_BITFVAL(FS453_PLLN_PLLN, pFs453Param[FS453_PARAM_PLL_N]);
Fs453WriteRegister(FS453_PLLN, &data); //0x2c
// ... Set PLLP
data = (CSP_BITFVAL(FS453_PLL_POSTDIV_PLL_EP, pFs453Param[FS453_PARAM_PLL_P_EP])|
CSP_BITFVAL(FS453_PLL_POSTDIV_PLL_IP, pFs453Param[FS453_PARAM_PLL_P_IP]));
Fs453WriteRegister(FS453_PLL_POSTDIV, &data); //0x0505
// ------------------------------------------------------------------------
// ------ Set UIM mode
/*
data = (CSP_BITFVAL(FS453_MISC_P_ORDER, FS453_SET_DISABLE)| // Only affects UIM is 11,12
CSP_BITFVAL(FS453_MISC_BRDG_RST,FS453_SET_DISABLE)| // Bridge pointer reset - disable
CSP_BITFVAL(FS453_MISC_UIM_E, FS453_SET_DISABLE)| // Change state at edge(0), at middle of pix(1)
CSP_BITFVAL(FS453_MISC_UV_SWAP, FS453_SET_ENABLE)| // Swap Cr(V) and Cb(U) internal input
CSP_BITFVAL(FS453_MISC_UIM_DEC, FS453_SET_DISABLE)| //horizontal prescaler divide by 2 to support high resolution VGA mode.
CSP_BITFVAL(FS453_MISC_UIM_CCLK,FS453_SET_DISABLE)| //inverts the edge on which input control is latched.
CSP_BITFVAL(FS453_MISC_UIM_DCLK,FS453_SET_DISABLE)| //inverts the edge on which input data is latched.
CSP_BITFVAL(FS453_MISC_UIM_MOD, FS453_MISC_UIM_MOD_N565));
Fs453WriteRegister(FS453_MISC, &data);
*/
// ------------------------------------------------------------------------
// ------ Set Video mode
// ...FS453 Video Output Modes
//
// VIDEO OUTPUT MODE | VID_MODE | EncMod | *MB | Sg0 | Sg1 | Sg2 | Sg3
// -----------------------------------------------------------------------
// Composite & S-Video | 0 | Normal | - | Y | C | GND | CVBS
// SDTV YPrPb | 1 | YUV | - | Y | Pr | Pb | CVBS
// SCART | 1 | Normal | - | GRN | R | BLU | CVBS
// HDTV YPrPb | 2 | -- | 0 | Y | Pr | Pb | GND
// VGA RGB | 2 | -- | 1 | GRN | RED | BLU | GND
//
// *MB: Matrix Bypasses
data = (CSP_BITFVAL(FS453_VID_CNTL0_TOP_FIELD, FS453_VID_CNTL0_TOP_FIELD_IS_LINE1)| // Selects the Interlaced HDTV Top Field.
CSP_BITFVAL(FS453_VID_CNTL0_OBIN_USIG, FS453_VID_CNTL0_OBIN_USIG_UNSIGNED)| // Input data in the YCrCb offset binary format, or in the RGB unsigned format.
CSP_BITFVAL(FS453_VID_CNTL0_PRPB_SYNC, FS453_SET_DISABLE)| // Inserts syncs on NOT ONLY Y, BUT Pr, and Pb components
CSP_BITFVAL(FS453_VID_CNTL0_VSYNC5_6, FS453_VID_CNTL0_VSYNC5_6_6HALF_LINES)|
CSP_BITFVAL(FS453_VID_CNTL0_BLANK_INV, FS453_SET_DISABLE)| // Disable - low active
CSP_BITFVAL(FS453_VID_CNTL0_FIELD_INV, FS453_SET_DISABLE)| // Disable - use if FIELD_MS is set to 0
CSP_BITFVAL(FS453_VID_CNTL0_VSYNC_INV, FS453_SET_ENABLE)| // Enable - input Vertical timing is measured with respect the failing edge of VSync
CSP_BITFVAL(FS453_VID_CNTL0_HSYNC_INV, FS453_SET_ENABLE)| // Enable - input Horizontal timing is measured with respect the failing edge of HSync
CSP_BITFVAL(FS453_VID_CNTL0_INT_PROG, FS453_SET_DISABLE)| // Disable - input image is NOT interlaced.
CSP_BITFVAL(FS453_VID_CNTL0_FIELD_MS, FS453_SET_ENABLE)| // Normally set to 0 for HDTV modes or 1 for SDTV modes
CSP_BITFVAL(FS453_VID_CNTL0_SYNC_LVL, FS453_SET_DISABLE)| // When set =1, HDTV sync amplitude is 300 mV, otherwise amplitude is 286 mV
CSP_BITFVAL(FS453_VID_CNTL0_SYNC_BI_TRI,FS453_SET_DISABLE)| // When set =1, inserts Bi-level HDTV syncs, otherwise inserts Tri-level syncs.
CSP_BITFVAL(FS453_VID_CNTL0_SYNC_ADD, FS453_SET_DISABLE)| // When set =1, inserts HDTV syncs.
CSP_BITFVAL(FS453_VID_CNTL0_MATRIX_BYP, FS453_SET_DISABLE)| // When set =1, bypasses RGB to YUV matrix
CSP_BITFVAL(FS453_VID_CNTL0_VID_MODE, FS453_VID_CNTL0_VID_MODE_COMPOSIT_SVIDEO)); // see above
Fs453WriteRegister(FS453_VID_CNTL0, &data); //0xb40//0x340
// ... update fs453 internal pll
m_fs453UpdatePLL();
// ------------------------------------------------------------------------
// ------ PLL
// ------------------------------------------------------------------------
// ------ Set flicker filter
// ... sharpness
data = CSP_BITFVAL(FS453_SHP_SHP, 0x0008); // off
Fs453WriteRegister(FS453_SHP, &data); //0x0008
// ... flicker
data = CSP_BITFVAL(FS453_FLK_FLK, 0x000C); // off
Fs453WriteRegister(FS453_FLK, &data); //0x000c
// ------------------------------------------------------------------------
// ------ Set luma/chroma filter
// ... Set Luma(Y) Notch
data = (CSP_BITFVAL(FS453_MISC_8D_NOTCH_EN, FS453_SET_DISABLE) | //Y Notch filter - off
CSP_BITFVAL(FS453_MISC_8D_NOTCH_WD, 0) | // 0 - narrow
CSP_BITFVAL(FS453_MISC_8D_NOTCH_FREQ, 0)); // 2 - NTSC, 5 - PAL
Fs453WriteRegister(FS453_MISC_8D, &data);
data = (CSP_BITFVAL(FS453_MISC_47_CHR_BW, FS453_FILTER_BANDWIDTH_NARROW) |
CSP_BITFVAL(FS453_MISC_47_COMP_YUV, FS453_MISC_47_COMP_YUV_YUV_OUTPUT) | // YUV out
CSP_BITFVAL(FS453_MISC_47_COMP_GAIN,FS453_MISC_47_COMP_GAIN_100));
//Fs453WriteRegister(FS453_MISC_47, &data);
data = (CSP_BITFVAL(FS453_MISC_74_UV_ORDER, 0) | //U/V swap - no
CSP_BITFVAL(FS453_MISC_74_PAL_MODE, FS453_SET_DISABLE) | // NTSC - disable, PAL - enable
CSP_BITFVAL(FS453_MISC_74_CHR_BW, FS453_FILTER_BANDWIDTH_NARROW) |
CSP_BITFVAL(FS453_MISC_74_INVERT_TOP,0) | // 0 - ntsc
CSP_BITFVAL(FS453_MISC_74_SYS625_50,FS453_SET_DISABLE) | // NTSC - disable, PAL - enable
CSP_BITFVAL(FS453_MISC_74_CH_PH_R, FS453_MISC_74_CH_PH_R_EVERY_4_FIELDS) |
CSP_BITFVAL(FS453_MISC_74_VSYNC5, FS453_SET_DISABLE)); // 6
//Fs453WriteRegister(FS453_MISC_74, &data); //0x02//0x04
if(mode == TVOUT_MODE_NTSC){
LONG w;
//HSync Width
data = 0x7e;
m_fs453WriteRegister ( 0x48, &data ,1);
//
data = 0x40; m_fs453WriteRegister ( 0x49, &data ,1);
data = 0x80; m_fs453WriteRegister ( 0x4A, &data ,1);
data = 62 + 5 ; m_fs453WriteRegister ( 0x4B, &data ,1);
data = 0x00; m_fs453WriteRegister ( 0x4C, &data ,1);
w= 235 ;//240
data = w >> 2 ; m_fs453WriteRegister ( 0x50, &data,1);
data = (w & 0x03) ; m_fs453WriteRegister( 0x65, &data, 1);
data = 0x13; m_fs453WriteRegister ( 0x69, &data ,1);
data = 0x2a; m_fs453WriteRegister ( 0x6C, &data ,1);
data = 0x14; m_fs453WriteRegister ( 0x73, &data ,1);
data = 0x04; m_fs453WriteRegister ( 0x74, &data ,1);
data = 0x10; m_fs453WriteRegister ( 0x75, &data ,1);
w=240;
data = (w >> 2) ; m_fs453WriteRegister ( 0x7C, &data,1);
data = (w & 0x03); m_fs453WriteRegister ( 0x7D, &data,1);
w=780;
data = (w >> 2) ; m_fs453WriteRegister ( 0x5E, &data, 1);
data = (w & 0x03); m_fs453WriteRegister ( 0x5F, &data, 1);
w=277;
data = (w >> 2) ; m_fs453WriteRegister ( 0x4E, &data, 1);
data = (w & 0x03); m_fs453WriteRegister ( 0x4F, &data, 1);
}
// ------------------------------------------------------------------------
// ------ Set DACs
data = (CSP_BITFVAL(FS453_DAC_CNTL_DAC_DMUX,FS453_DAC_CNTL_DAC_MUX_SIGNAL3) | // DACD - composite
CSP_BITFVAL(FS453_DAC_CNTL_DAC_CMUX,FS453_DAC_CNTL_DAC_MUX_SIGNAL2) | // DACC - x
CSP_BITFVAL(FS453_DAC_CNTL_DAC_BMUX,FS453_DAC_CNTL_DAC_MUX_SIGNAL1) | // DACB - C(S-Video)
CSP_BITFVAL(FS453_DAC_CNTL_DAC_AMUX,FS453_DAC_CNTL_DAC_MUX_SIGNAL0)); // DACA - Y(S-Video)
Fs453WriteRegister(FS453_DAC_CNTL, &data);
// ------------------------------------------------------------------------
// ------ Issue Bridge Reset
data = (CSP_BITFVAL(FS453_MISC_P_ORDER, FS453_SET_DISABLE)| // Only affects UIM is 11,12
CSP_BITFVAL(FS453_MISC_BRDG_RST,FS453_SET_ENABLE)| // Bridge pointer reset - disable
CSP_BITFVAL(FS453_MISC_UIM_E, FS453_SET_DISABLE)| // Change state at edge(0), at middle of pix(1)
CSP_BITFVAL(FS453_MISC_UV_SWAP, FS453_SET_ENABLE)| // Swap Cr(V) and Cb(U) internal input
CSP_BITFVAL(FS453_MISC_UIM_DEC, FS453_SET_DISABLE)| //horizontal prescaler divide by 2 to support high resolution VGA mode.
CSP_BITFVAL(FS453_MISC_UIM_CCLK,FS453_SET_DISABLE)| //inverts the edge on which input control is latched.
CSP_BITFVAL(FS453_MISC_UIM_DCLK,FS453_SET_DISABLE)| //inverts the edge on which input data is latched.
CSP_BITFVAL(FS453_MISC_UIM_MOD, FS453_MISC_UIM_MOD_N565));
Fs453WriteRegister(FS453_MISC, &data);
//Sleep(1000);
data &= ~(CSP_BITFMASK(FS453_MISC_BRDG_RST));
data |= CSP_BITFVAL(FS453_MISC_BRDG_RST, FS453_SET_DISABLE);
rc = Fs453WriteRegister(FS453_MISC, &data);
rc = TRUE;
return rc;
}
//-----------------------------------------------------------------------------
//
// Function: Fs453DACOn
//
// This function enable DAC of FS453.
//
// Parameters:
// None.
//
// Returns:
// Returns TRUE if successful, otherwise returns FALSE.
//
//-----------------------------------------------------------------------------
BOOL Fs453DACOn(TVOUT_DAC dac)
{
BOOL rc = FALSE;
DWORD data;
// ------------------------------------------------------------------------
// ------ Power on DACs
data = ( CSP_BITFVAL(FS453_PWR_MGNT_GTLIO_PD, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_PLL_PD, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_CLKOFF, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_CLK_SOFF, FS453_PWR_MGNT_CLK_SOFF_HDTV_CLK_OFF) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_D_LP, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_C_LP, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_B_LP, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_A_LP, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_BGAP_OFF, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_D_OFF, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_C_OFF, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_B_OFF, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_A_OFF, FS453_SET_DISABLE) );
rc = Fs453WriteRegister(FS453_PWR_MGNT, &data); //0x202//data = 0x0204
return rc;
}
//-----------------------------------------------------------------------------
//
// Function: Fs453DACOff
//
// This function disables DAC of FS453.
//
// Parameters:
// None.
//
// Returns:
// Returns TRUE if successful, otherwise returns FALSE.
//
//-----------------------------------------------------------------------------
BOOL Fs453DACOff(TVOUT_DAC dac)
{
BOOL rc = FALSE;
DWORD data;
// Power on DACs
data = ( CSP_BITFVAL(FS453_PWR_MGNT_GTLIO_PD, FS453_SET_DISABLE) | //GTLIO power down mode
CSP_BITFVAL(FS453_PWR_MGNT_PLL_PD, FS453_SET_DISABLE) | // PLL power donw mode
CSP_BITFVAL(FS453_PWR_MGNT_CLKOFF, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_CLK_SOFF, FS453_PWR_MGNT_CLK_SOFF_HDTV_CLK_OFF) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_D_LP, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_C_LP, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_B_LP, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_A_LP, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_BGAP_OFF, FS453_SET_DISABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_D_OFF, FS453_SET_ENABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_C_OFF, FS453_SET_ENABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_B_OFF, FS453_SET_ENABLE) |
CSP_BITFVAL(FS453_PWR_MGNT_DAC_A_OFF, FS453_SET_ENABLE) );
rc = Fs453WriteRegister(FS453_PWR_MGNT, &data); //data = 0x020F
return rc;
}
//-----------------------------------------------------------------------------
//
// Function: Fs453Deinit
//
// This function maps the peripheral registers of the audio devices for
// direct access by the driver.
//
// Parameters:
// None.
//
// Returns:
// Returns TRUE if successful, otherwise returns FALSE.
//
//-----------------------------------------------------------------------------
BOOL Fs453Deinit(void)
{
// Close TV, if I2C is available
;
// Release I2C
if(m_hI2C != NULL)
{
CloseHandle(m_hI2C);
m_hI2C = NULL;
}
return TRUE;
}
//
BOOL Fs453ColorBarOn(void)
{
BOOL rc;
DWORD data = 0x02;
rc = Fs453WriteRegister(FS453_MISC_45, &data); //data = 0x02
return rc;
}
#ifndef __cplusplus
}
#endif
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