encregdrv2.c

freescale i.mx31 BSP CE5.0全部源码

/*------------------------------------------------------------------------------
--                                                                            --
--       This software is confidential and proprietary and may be used        --
--        only as expressly authorized by a licensing agreement from          --
--                                                                            --
--                            Hantro Products Oy.                             --
--                                                                            --
--      In the event of publication, the following notice is applicable:      --
--                                                                            --
--                   (C) COPYRIGHT 2003 HANTRO PRODUCTS OY                    --
--                            ALL RIGHTS RESERVED                             --
--                                                                            --
--          The entire notice above must be reproduced on all copies.         --
--                                                                            --
--------------------------------------------------------------------------------
--
--  Abstract : Encoder HW register access functions
--
-------------------------------------------------------------------------------*/

#include "ewl.h"
#include "basetype.h"
#include "encregdrv.h"
#include "EncSim.h"

/* 1. (AMBAIFE) Encoder Register Offsets   */

#define ENCREG(nr)  (nr<<2)

/* 2. Mask fields */
#define mask_1b         (u32)0x00000001
#define mask_2b         (u32)0x00000003
#define mask_3b         (u32)0x00000007
#define mask_4b         (u32)0x0000000F
#define mask_5b         (u32)0x0000001F
#define mask_6b         (u32)0x0000003F
#define mask_8b         (u32)0x000000FF
#define mask_16b        (u32)0x0000FFFF

/* 3. Encoder register access drivers */

/******************************************************************************/
/********************** ENCODER REGISTER (BASE + 0x0C) ************************/
/******************************************************************************/

/*******************************************************************************
 Function name   : SetEncStrmBuf3Lim
 Description     : Set the initial limit in the DCT stream buffer when the
                   VOP should be discarded.
 Return type     : void 
 Argument        : u32 offset
*******************************************************************************/
void SetEncStrmBuf3Lim(u32 offset)
{
    u32 val;

    ASSERT(offset < (1 << 16));

    val = EWL_ReadReg(0x0C);
    val = (val & ~(mask_16b << 16)) | (offset << 16);
    EWL_WriteReg(0x0C, val);
}

/*******************************************************************************
 Function name   : GetEncStrmBuf3Lim
 Description     : Get the current limit in the DCT stream buffer
 Return type     : u32 
*******************************************************************************/
u32 GetEncStrmBuf3Lim()
{
    u32 val;

    val = EWL_ReadReg(0x0C);
    val = (val >> 16);
    return val;
}

/*******************************************************************************
 Function name   : SetEncStrmBuf1Lim
 Description     : Set the limit in the final stream buffer
 Return type     : void 
 Argument        : u32 offset
*******************************************************************************/
void SetEncStrmBuf1Lim(u32 offset)
{
    u32 val;

	/* 2006/05/31 vira: It is ok if the user has defined larger than 2^16 byte
	   buffer, but we use at maximum only 2^16 byte of the buffer */
	if(offset >= (1 << 16))
		offset = 0xFFFF;

    ASSERT(offset < (1 << 16));

    val = EWL_ReadReg(0x0C);
    val = (val & ~mask_16b) | (offset);
    EWL_WriteReg(0x0C, val);
}

/*******************************************************************************
 Function name   : GetEncStrmBuf1Lim
 Description     : Get the limit in the final stream buffer
 Return type     : u32 
*******************************************************************************/
u32 GetEncStrmBuf1Lim()
{
    u32 val;

    val = EWL_ReadReg(0x0C);
    val = (val & mask_16b);
    return val;
}

/******************************************************************************/
/********************** ENCODER REGISTER (BASE + 0x10) ************************/
/******************************************************************************/

/*******************************************************************************
 Function name   : SetEncIrqClr
 Description     : Clear the IRQ line
 Return type     : void 
*******************************************************************************/
void SetEncIrqClr()
{
    u32 val;

    val = EWL_ReadReg(0x10);
    val = val & (~mask_1b);
    EWL_WriteReg(0x10, val);
}

/*******************************************************************************
 Function name   : SetEncStrmStatClr
 Description     : Clear the stream status
 Return type     : void 
*******************************************************************************/
void SetEncStrmStatClr()
{
    u32 val;

    val = EWL_ReadReg(0x10);
    val = val & ~(mask_1b << 2);
    EWL_WriteReg(0x10, val);
}

/*******************************************************************************
 Function name   : GetEncStrmStat
 Description     : Get the stream status
 Return type     : u32
                   0    No stream was generated after previous interrupt
                   1    Stream was generated after previous interrupt
*******************************************************************************/
u32 GetEncStrmStat()
{
    u32 val;

    val = EWL_ReadReg(0x10);
    val = (val >> 2) & mask_1b;
    return val;
}

/*******************************************************************************
 Function name   : SetEncEnable
 Description     : Enable/Disable ASIC
 Return type     : void 
 Argument        : u32 enable
*******************************************************************************/
void SetEncEnable(u32 enable)
{
    u32 val;

    if(enable)
    {
        /* enable ASIC clock */
        val = EWL_ReadReg(0x0);
        val = val | (mask_1b << 12);
        EWL_WriteReg(0x0, val);
        
        /* enable ASIC */
        val = EWL_ReadReg(0x10);
        val = val | (mask_1b << 1);
        EWL_WriteReg(0x10, val);
    }
    else
    {
        /* disable ASIC first */
        val = EWL_ReadReg(0x10);
        val = val & ~(mask_1b << 1);
        EWL_WriteReg(0x10, val);

        SetEncIrqClr(); /* clear any IRQ */
        SetEncIrqStatClr(IRQ_ALL);  /* clear pause status */
    }

}

/*******************************************************************************
 Function name   : GetEncEnaStat
 Description     : Get ASIC's enable status
 Return type     : u32 
*******************************************************************************/
u32 GetEncEnaStat()
{
    u32 val;

    val = EWL_ReadReg(0x10);
    val = (val >> 1) & mask_1b;
    return val;
}

/*******************************************************************************
 Function name : SetEncHWIrqEnable
 Description   : Enabel/Disable the HW interrupt generation
 Return type   : void 
 Argument      : u32 error_irq - non zero to enable the error IRQ
 Argument      : u32 enc_irq - non zero to enable the encoder IRQ
*******************************************************************************/
void SetEncHWIrqEnable(u32 error_irq, u32 enc_irq)
{
    u32 val;

    val = EWL_ReadReg(0x10);

    if(error_irq != 0)
        val = val | (mask_1b << 8);
    else
        val = val & ~(mask_1b << 8);

    if(enc_irq != 0)
        val = val | (mask_1b << 7);
    else
        val = val & ~(mask_1b << 7);

    EWL_WriteReg(0x10, val);
}

/*******************************************************************************
 Function name   : GetEncHWIrqEnable
 Description     : Get the IRQ enable status
 Return type     : u32 
*******************************************************************************/
u32 GetEncHWIrqEnable()
{
    u32 val;

    val = EWL_ReadReg(0x10);
    val = (mask_2b & (val >> 7));
    return val;
}

/*******************************************************************************
 Function name   : SetEncIrqStatClr
 Description     : Clear the IRQ status bits
 Return type     : void 
*******************************************************************************/
void SetEncIrqStatClr(u32 mask)
{
    u32 val;
    
    if ((mask & IRQ_VOP_RDY) == IRQ_VOP_RDY)
    {
        /* disable ASIC clock when the VOP is ready */
        val = EWL_ReadReg(0x0);
        val = val & ~(mask_1b << 12);
        EWL_WriteReg(0x0, val);
    }

    val = EWL_ReadReg(0x10);
    val = val & (~((mask & mask_4b) << 3));
    EWL_WriteReg(0x10, val);
}

/*******************************************************************************
 Function name   : GetEncIrqStat
 Description     : Get the IRQ status
 Return type     : u32 
*******************************************************************************/
u32 GetEncIrqStat()
{
    u32 val;

    val = EWL_ReadReg(0x10);
    val = (mask_4b & (val >> 3));
    return val;
}

/*******************************************************************************
 Function name   : SetEncMbsInCol
 Description     : Set the picture height in macroblocks
 Return type     : void 
 Argument        : u32 mbs
*******************************************************************************/
void SetEncMbsInCol(u32 mbs)
{
    u32 val;

    ASSERT(mbs >= 6 && mbs <= 30);

    val = EWL_ReadReg(0x10);
    val = (val & ~(mask_5b << 10)) | (mbs << 10);