bspserial.c

freescale i.mx31 BSP CE5.0全部源码

//-----------------------------------------------------------------------------
//
//  Copyright (C) 2004, Motorola Inc. All Rights Reserved
//
//-----------------------------------------------------------------------------
//
//  Copyright (C) 2004, Freescale Semiconductor, Inc. All Rights Reserved
//  THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
//  BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
//  FREESCALE SEMICONDUCTOR, INC.
//
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
//
//  File:  bspserial.c
//
//  Provides BSP-specific configuration routines for the UART peripheral.
//
//-----------------------------------------------------------------------------
#include <windows.h>
#include "bsp.h"
#include "uart.h"

//-----------------------------------------------------------------------------
// External Functions

//-----------------------------------------------------------------------------
// External Variables

//-----------------------------------------------------------------------------
// Defines

#define UART_MAX_DIV            7

#define SERIAL_SDMA_RX_BUFFER_SIZE 0x200
#define SERIAL_SDMA_TX_BUFFER_SIZE 0x400

//-----------------------------------------------------------------------------
// Types

//-----------------------------------------------------------------------------
// Global Variables

//-----------------------------------------------------------------------------
// Local Variables

//------------------------------------------------------------------------------
// Local Functions

//-----------------------------------------------------------------------------
//
// Function: BSPUartCalRFDIV
//
// This is a private function to calculate the data
// rate divider from input frequency.
//
// Parameters:
//      dwFrequency
//          [in] Frequency requested.
//
// Returns:
//      Data rate divisor for requested frequency.
//-----------------------------------------------------------------------------
UCHAR BSPUartCalRFDIV( ULONG* pRefFreq )
{
    UCHAR dwDivisor; // the data rate divisor
    UINT32 freq;

    DDKClockGetFreq(DDK_CLOCK_SIGNAL_PER, &freq);
    dwDivisor =(UCHAR) (freq / *pRefFreq);

    if (dwDivisor == 0)
        dwDivisor = 1;
    else if (dwDivisor > UART_MAX_DIV)
        dwDivisor = UART_MAX_DIV;

    *pRefFreq = freq /dwDivisor;

    return dwDivisor;
}

#if 0
//-----------------------------------------------------------------------------
//
// Function: BSPUartGetIrq
//
// This is a private function to get the UART irq No with specified Uart IO address.
//
// Parameters:
//      HWAddr
//          [in] Physical IO address.
//
// Returns:
//      corresponding uart type.
//-----------------------------------------------------------------------------
BOOL BSPUartGetIrq(ULONG HWAddr, PULONG pIrq)
{
    switch (HWAddr) {
        case CSP_BASE_REG_PA_UART1:
            *pIrq = IRQ_UART1;
            return TRUE;
        case CSP_BASE_REG_PA_UART2:
            *pIrq = IRQ_UART2;
            return TRUE;
        case CSP_BASE_REG_PA_UART3:
            *pIrq = IRQ_UART3;
            return TRUE;
		
		case CSP_BASE_REG_PA_UART4:
            *pIrq = IRQ_UART4;
            return TRUE;
		case CSP_BASE_REG_PA_UART5:
            *pIrq = IRQ_UART5;
            return TRUE;

        default:
            return FALSE;
    }
}
#endif

//-----------------------------------------------------------------------------
//
// Function: BSPUartGetType
//
// This is a private function to get the UART type with specified Uart IO address.
//
// Parameters:
//      HWAddr
//          [in] Physical IO address.
//
// Returns:
//      corresponding uart type.
//-----------------------------------------------------------------------------
BOOL BSPUartGetType(ULONG HWAddr, uartType_c * pType)
{
    switch (HWAddr) {
        case CSP_BASE_REG_PA_UART1:
            *pType=DCE;
            return TRUE;
        case CSP_BASE_REG_PA_UART2:
            *pType=DTE;
            return TRUE;
        case CSP_BASE_REG_PA_UART3:
            *pType=DTE;
            return TRUE;
        case CSP_BASE_REG_PA_UART4:
            *pType=DTE;
            return TRUE;
        case CSP_BASE_REG_PA_UART5:
            *pType=DTE;
            return TRUE;
        default:
            return FALSE;
    }
}


//-----------------------------------------------------------------------------
//
// Function: BSPUartEnableClock
//
// This function is a wrapper for Uart to enable/disable its clock using a valid
// CRM handle.
//
// Parameters:
//      HWAddr
//          [in] Physical IO address.
//      bEnable
//          [in] TRUE if Uart Clock is to be enabled. FALSE if Uart Clock is
//                to be disabled.
//
// Returns:
//      TRUE if successfully performed the required action.
//
//-----------------------------------------------------------------------------
BOOL BSPUartEnableClock(ULONG HWAddr, BOOL bEnable)
{
    BOOL result = FALSE;
    DDK_CLOCK_GATE_INDEX cgIndex;

    switch (HWAddr) {
        case CSP_BASE_REG_PA_UART1:
            cgIndex=DDK_CLOCK_GATE_INDEX_UART1;
            break;
        case CSP_BASE_REG_PA_UART2:
            cgIndex=DDK_CLOCK_GATE_INDEX_UART2;
            break;
        case CSP_BASE_REG_PA_UART3:
            cgIndex=DDK_CLOCK_GATE_INDEX_UART3;
            break;
        case CSP_BASE_REG_PA_UART4:
            cgIndex=DDK_CLOCK_GATE_INDEX_UART4;
            break;
        case CSP_BASE_REG_PA_UART5:
            cgIndex=DDK_CLOCK_GATE_INDEX_UART5;
            break;
        default:
            return result;
    }

    if (bEnable)
        result = DDKClockSetGatingMode(cgIndex, DDK_CLOCK_GATE_MODE_ENABLED_ALL);
    else
        result = DDKClockSetGatingMode(cgIndex, DDK_CLOCK_GATE_MODE_DISABLED);

    return result;
}

VOID BSPUartConfigTranceiver(ULONG HWAddr,BOOL bEnable)
{
	PHYSICAL_ADDRESS phyAddr = {BSP_BASE_REG_PA_PBC_BASE, 0};
	PCSP_PBC_REGS g_pPBC;

	// Map PBC registers to virtual address space
	g_pPBC = (PCSP_PBC_REGS) MmMapIoSpace(phyAddr, sizeof(CSP_PBC_REGS), FALSE);
	if (g_pPBC == NULL)
	{
		return ;
	}

	if(bEnable)
	{
		switch (HWAddr) {
			case CSP_BASE_REG_PA_UART1:
				
				//Map UART1 to UART C
				OUTREG16(&g_pPBC->BCTRL2_SET,  (1 << PBC_BCTRL2_USELC_LSH));
				//Enable UART C
				OUTREG16 (&g_pPBC->BCTRL1_CLEAR, (1 << PBC_BCTRL1_CLEAR_UENCE_LSH));
				//Enable UART C MODEM
				OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_UMODENC_LSH));

				/*
				//Map UART1 to UART A
				OUTREG16(&g_pPBC->BCTRL2_CLEAR,  (1 << PBC_BCTRL2_USELA_LSH));
				//Enable UART A
				OUTREG16 (&g_pPBC->BCTRL1_CLEAR,  (1 << PBC_BCTRL1_CLEAR_UENA_LSH));
				//Enable UART A MODEM
				OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_UMODENA_LSH));
				*/

				break;
			
			case CSP_BASE_REG_PA_UART2:

				/*
				//Map UART2 to UART C
				OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_USELC_LSH));
				//Enable UARTC
				OUTREG16 (&g_pPBC->BCTRL1_CLEAR, (1 << PBC_BCTRL1_CLEAR_UENCE_LSH));
				//Enable UART C MODEM
				OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_UMODENC_LSH));
				*/
				break;

			case CSP_BASE_REG_PA_UART3:
				
				//Map UART3 to UART B
				OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_USELB_LSH));
				//Enable UARTB
				OUTREG16 (&g_pPBC->BCTRL1_CLEAR, (1 << PBC_BCTRL1_CLEAR_UENB_LSH));
				break;

			 case CSP_BASE_REG_PA_UART4:

				 //Map UART4 to UART B
				 OUTREG16(&g_pPBC->BCTRL2_SET, (1 << PBC_BCTRL2_USELB_LSH));
				 //Enable UART B
				 OUTREG16 (&g_pPBC->BCTRL1_CLEAR, (1 << PBC_BCTRL1_CLEAR_UENB_LSH));
				 break;

			case CSP_BASE_REG_PA_UART5:

				//Map UART5 to UART A
				OUTREG16(&g_pPBC->BCTRL2_SET,  (1 << PBC_BCTRL2_USELA_LSH));
				//Enable UART A
				OUTREG16 (&g_pPBC->BCTRL1_CLEAR, (1 << PBC_BCTRL1_CLEAR_UENA_LSH));
				//Enable UART A MODEM
				OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_UMODENA_LSH));
				break;
		}
	}
	else 
	{
		switch (HWAddr) {
			case CSP_BASE_REG_PA_UART1:

				//Reset UART C
				OUTREG16(&g_pPBC->BCTRL2_SET,  (1 << PBC_BCTRL2_USELC_LSH));
				//Disable UART C
				OUTREG16 (&g_pPBC->BCTRL1_SET, (1 << PBC_BCTRL1_CLEAR_UENCE_LSH));
				//Disable UART C MODEM
				//OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_UMODENC_LSH));

				/*
				//Reset UART A
				OUTREG16(&g_pPBC->BCTRL2_SET,  (1 << PBC_BCTRL2_USELA_LSH));
				//Disable UART A
				OUTREG16 (&g_pPBC->BCTRL1_SET,  (1 << PBC_BCTRL1_CLEAR_UENA_LSH));
				//Disable UART A MODEM
				OUTREG16(&g_pPBC->BCTRL2_SET, (1 << PBC_BCTRL2_UMODENA_LSH));
				*/
				break;
			
			case CSP_BASE_REG_PA_UART2:

				/*
				//Reset UART C
				OUTREG16(&g_pPBC->BCTRL2_SET, (1 << PBC_BCTRL2_USELC_LSH));
				//Disable UARTC
				OUTREG16 (&g_pPBC->BCTRL1_SET, (1 << PBC_BCTRL1_CLEAR_UENCE_LSH));
				//Disable UART C MODEM
				OUTREG16(&g_pPBC->BCTRL2_CLEAR, (1 << PBC_BCTRL2_UMODENC_LSH));
				*/