startup.s

freescale i.mx31 BSP CE5.0全部源码

;******************************************************************************
;*
;* Copyright (c) Microsoft Corporation.  All rights reserved.
;*
;* Use of this source code is subject to the terms of the Microsoft end-user
;* license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
;* If you did not accept the terms of the EULA, you are not authorized to use
;* this source code. For a copy of the EULA, please see the LICENSE.RTF on your
;* install media.
;*
;******************************************************************************
;*
;* Copyright (C) 2004, Motorola Inc. All Rights Reserved
;*
;******************************************************************************
;*
;* Copyright (C) 2004, Freescale Semiconductor, Inc. All Rights Reserved
;* THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
;* BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
;* FREESCALE SEMICONDUCTOR, INC.
;*
;******************************************************************************

;******************************************************************************
;*
;* FILE:    startup.s
;*
;* PURPOSE: This module includes OAL startup.s to provide platform initialization.
;*          After platform initialization, this module relocates the bootloader
;*          to ram and enables virtual memory.
;*
;*          The Launch function disables virtual memory and invokes the kernel
;*          startup.
;*
;******************************************************************************

    GBLL    BOOTLOADER
BOOTLOADER   SETL    {TRUE}


    INCLUDE ..\\..\\..\\..\\src\\kernel\\oal\\startup.s

; Flash Physical base address defines
FlashPABase             EQU        CSP_BASE_MEM_PA_CS0
FlashVABase             EQU        0x80000000
RamPABase                EQU        CSP_BASE_MEM_PA_CSD0
RamVABase                 EQU        0x88000000

; Physical ram address/size of bootloader image
; Do not change these unless eboot.bib is changed!
EbootRamOffset            EQU        0x00040000
EbootImageSize            EQU        0x00040000  ; max size of Eboot image
EbootFlashPAStart        EQU        (FlashPABase)
EbootFlashVAStart        EQU     (FlashVABase)
EbootRamPAStart            EQU        (RamPABase + EbootRamOffset) ; PA of Eboot
EbootRamVAStart         EQU     (RamVABase + EbootRamOffset) ; VA of Eboot

; Physical ram address/size of page tables
MmuPageTableOffset        EQU        0x0003C000
MmuPageTableBase        EQU     (RamPABase + MmuPageTableOffset)  ; PA of TTB in ram

; End of stack VA, used after MMU enabled
StackOffset                EQU        0x0003C000
StackEnd                EQU        (RamVABase +StackOffset)

    IMPORT    BootloaderMain

;******************************************************************************
;*
;* FUNCTION:    KernelStart
;*
;* DESCRIPTION: Entry point for initializing bootloader to execute from ram
;*              in virtual address mode.
;*              Mimics the kernel start function name to reduce conditional
;*              code between bootloader and kernel boot.
;*
;* PARAMETERS:  None
;*
;* RETURNS:     None
;*
;******************************************************************************

    LEAF_ENTRY KernelStart

    ; Relocate the eboot image to ram if running in flash
    mov     r0, pc
    ldr     r1, =FlashPABase
    cmp     r0, r1
    blt     RamStart    ; skip relocation if already in ram

    ; Skip reloation if we are running from PSRAM
    ldr     r1, =0xB5000000
    cmp     r0, r1
    bge     RamStart

    ldr        r1, =FlashPABase
    ldr        r0, =EbootRamPAStart
    ldr        r2, =(EbootImageSize/16)

10
    ldmia   r1!, {r3-r6}
    stmia   r0!, {r3-r6}
    subs    r2, r2, #1
    bne     %b10

20
    adr     r2, RamStart
    ldr     r3, =(FlashPABase)
    sub     r3, r2, r3
    ldr     r4, =(EbootRamPAStart)
    add     r2, r4, r3

    IF Interworking :LOR: Thumbing
        bx  r2
    ELSE
          mov pc, r2          ; return
    ENDIF

RamStart
    ; Eboot now running in ram

    ; set up lr for return in virtual space
    adr     r2, MMUSetupDone
    ldr     r3, =(EbootRamPAStart)
    sub     r2, r2, r3
    ldr     r3, =(EbootRamVAStart)
    add     r2, r2, r3
    mov        lr, r2

    ; Load address of OEMAddressTable into r0
    adrl     r0, g_oalAddressTable

    ; Load base address of page tables into r1
    ldr     r1, =(MmuPageTableBase)

    ; Branch to set up MMU & enable caches
    ; to avoid SDRAM multiple read failure
    b       mmuSetup
    nop
    nop
    nop
    nop
    nop

    ; We're now in virtual address space!!
MMUSetupDone
      ; Set up the pointer to external SDRAM
    ldr     sp, =(StackEnd-4)

    ; branch to BootloaderMain
    b       BootloaderMain

SpinHere
    ; should never reach here
    b         SpinHere


;******************************************************************************
;*  FUNCTION:       void mmuSetup(UINT32 *OEMAddressMap, UINT32 tableBase)
;*
;*  DESCRIPTION:    This function is called by StartUp and does the
;*                    following:
;*                   Sets up MMU according to MMU page table.
;*                   Enables MMU, I, D cache
;*                   Used only in bootloader.
;*
;*  PARAMETERS:     OEMAddressMap - ptr to OEMAddressMap
;*                  tablebase - address of translation table base
;*
;*  RETURNS:        None
;*
;******************************************************************************

;;    LEAF_ENTRY    mmuSetup

mmuSetup
    mov     r11, r0                     ; (r11) = &MemoryMap (save pointer)
    mov     r9, r1                      ; (r9) = Physical translation table base

    ;  Set translation table base
    ldr     r0, =0xFFFFC000
    and     r9, r9, r0                  ; TTB must be on 16kB boundary
    mcr     p15, 0, r9, c2, c0, 0       ; set translation table base

    mov     r0, #0
    add     r2, r1, #0x4000             ; r2 = end of page tables

    ; Zero out translation tables
9
    str     r0, [r1], #4
    cmp     r1, r2
    bne     %B9

    ; Read OEMAddressTable[] row by row
    ;
    ; r2 temporarily holds OEMAddressTable[VA]
    ; r3 temporarily holds OEMAddressTable[PHY]
    ; r4 temporarily holds OEMAddressTable[#MB]
    mov     r0, #0x0A            ; (r0) = Section (1MB) Descriptor; C=1 B=0.  Write-thru cache mode
    orr     r0, r0, #0x400        ; set AP
14
    mov     r1, r11             ; (r1) = ptr to MemoryMap array

15
    ldr        r2, [r1], #4        ; r2 = virtual cached address of bank
    ldr        r3, [r1], #4        ; r3 = physical address of bank
    ldr        r4, [r1], #4        ; r4 = size of bank in MB

    cmp     r4, #0          ; reached end of table?
    beq     %F34

    ; r2 = address in descriptor
    ; r0 = actual section descriptor
        
    ; Create the address in Descriptor
    ldr     r6, =0xFFF00000
    and     r2, r2, r6              ; VA[31:20] = table index for section descriptor
    orr     r2, r9, r2, LSR #18     ; r2 = (TTB[31:14] | VA[31:20] >> 18)
        
    ; Create the actual section descriptor
    ldr     r6, =0xFFF00000
    and     r3, r3, r6              ; only PA[31:20] are valid
    orr     r0, r3, r0              ; build the descriptor: r0 = (PA[31:20] | the rest of the descriptor)

    ; Store the descriptor at the proper (phy) address
    ;
26
    str     r0, [r2], #4
    add     r0, r0, #0x00100000     ; (r0) = THE Section descriptor for the next 1MB mapping (just add 1MB)
        
    sub     r4, r4, #1              ; Decrement number of MB left 
    cmp     r4, #0
    bne     %B26                    ; Map next MB


    bic     r0, r0, #0xF0000000     ; Clear Section Base Address Field
    bic     r0, r0, #0x0FF00000     ; Clear Section Base Address Field
    b       %B15                    ; Get and process next table element                

    ;
    ;  Next, go through the above loop construct again.
    ;  This time, we will map C=B=0 space (i.e. uncached, nonbuffered)
    ;
34
    tst        r0, #8                  ; Test for 'C' bit set
    bic        r0, r0, #0x0C           ; Clear C, B bits in Descriptor
        
    add        r9, r9, #0x0800         ; r9 = ptr to 1st PTE for "unmapped uncached space" (0x2000 0000 + V_U_Adx)
    bne        %B14                    ; setup descriptors for uncached space

    sub        r9, r9, #0x3000        ; (r10) = restore address of 1st level page table

ActivateMMU
    ; level 1 descriptors are set up. Activate MMU and caches.
    mov     r1, #1
    mcr     p15, 0, r1, c3, c0, 0   ; setup access to domain 0
    mov     r0, #0
    mcr     p15, 0, r0, c8, c7, 0   ; flush I+D TLBs
    mcr     p15, 0, r0, c7, c10, 4  ; drain write and fill buffers
        
    mov     r1, #0x78               ; bits [6:3] must be written as 1's
    orr     r1, r1, #0x1            ; Enable: MMU
    orr     r1, r1, #0x1000         ; Enable I cache
    orr     r1, r1, #0x4            ; Enable D Cache
    
    cmp     lr, #0                  ; make sure no stall on below
    mcr        p15, 0, r1, c1, c0, 0    ; MMU ON:  All mem accesses now ~Virtual~

    IF Interworking :LOR: Thumbing
        bx  lr
    ELSE
          mov pc, lr          ; return
    ENDIF

;******************************************************************************
;*  FUNCTION:       void Launch (UINT32 *LaunchAddress);
;*
;*  DESCRIPTION:    This function is called by OEMLaunch and does the 
;*                    following:
;*                   Disables MMU
;*                   Invalidates I, D cache
;*                   Invalidates TLB
;*                   Used only in bootloader. 
;*
;*  PARAMETERS:     LaunchAddress - function pointer to transfer execution     
;*
;*  RETURNS:        None
;*
;******************************************************************************

    LEAF_ENTRY Launch
    
    IF {FALSE}
    ldr     r1, =RamVABase
;    ldr        r2, =PhysicalStart      ; This is virtual address
    cmp     r2, r1
    bgt        %f5
    
    ldr     r3, =FlashVABase
    sub     r2, r2, r3              ; Get the offset from kernel ram image
    ldr     r3, =FlashPABase
    b        %f10

5
    ELSE
    adr        r2, PhysicalStart      ; This is virtual address
;;    ldr        r2, =(PhysicalStart)      ; This is virtual address
    ENDIF
    ldr     r3, =(RamVABase)
    sub     r2, r2, r3              ; Get the offset from eboot ram image
    ldr     r3, =(RamPABase)

10
    add     r2, r2, r3              ; Get PA of PhysicalStart

    mov     r1, #0
    mcr        p15, 0, r1, c7, c7, 0    ; Invalidate the I, D cache
    mcr        p15, 0, r1, c7, c10, 4    ; Drain write buffer
    mcr        p15, 0, r1, c8, c7, 0   ; Invalidate TLB

    mov     r1, #0x0078             
    mcr     p15, 0, r1, c1, c0, 0   ; Disable MMU, caches and write buffer

    mov     pc, r2                  ; Jump to PhysicalStart

    nop                             ; These NOPs are used to flush the Pipeline
    nop
    nop
    nop

PhysicalStart
    mov     r1, #0
    mcr        p15, 0, r1, c7, c7, 0    ; Invalidate the I, D cache
    mcr        p15, 0, r1, c7, c10, 4    ; Drain write buffer
    mcr        p15, 0, r1, c8, c7, 0   ; Invalidate TLB

    mov     pc, r0                  ; Jump to launch address! 

LaunchFail
    ; should never reach here
    b         LaunchFail
    
    ENTRY_END    Launch

    END