nandloader.s

freescale i.mx31 BSP CE5.0全部源码

;******************************************************************************
;*
;* Copyright (C) 2004, Motorola Inc. All Rights Reserved
;*
;******************************************************************************
;*
;* Copyright (C) 2004, Freescale Semiconductor, Inc. All Rights Reserved
;* THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
;* BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
;* FREESCALE SEMICONDUCTOR, INC.
;*
;******************************************************************************

;******************************************************************************
;
; File:		NANDLOADER/nandloader.s
; Purpose:	Implements the initial boot loader for NAND boot. It is
;			automatically loader by NANDFC into a 2k RAM buffer upon startup.
;			This copies the 256kB EBOOT into ram and jumps there.
;
; Notes:	This bases on the assumption that block 0 is a good block.
;
; Date:	   	03/23/2004
;
;******************************************************************************

    AREA    Init, CODE, READONLY, ALIGN=9	; (ALIGN=9 needed for ALIGN 0x0200 below)

	OPT    2                           ; disable listing
	INCLUDE     nand.h
	OPT    1                           ; reenable listing

	OPT    2                           ; disable listing
	INCLUDE     registers.h
	OPT    1                           ; reenable listing

; The following should not be changed unless config.bib &
; eboot.bib are changed!
; Flash/RAM Physical/Virtual base addresses
RamPABase 				EQU		CSP_BASE_MEM_PA_CSD0  ; PA of RAM
StackEndInRamOffset		EQU		0x0003C000	; end of stack area offset
EbootInRamOffset		EQU		0x00040000	; start of EBOOT area
IPLRelocateRamOffset	EQU		0x00008000	; location to relocate IPL to

	IF :LNOT: :DEF: RELOCATE_IPL
	GBLL	RELOCATE_IPL
RELOCATE_IPL	SETL	{TRUE}
	ENDIF
;
;------------------------------------------------------------------------------
;   CODE AREA
;------------------------------------------------------------------------------

MAIN
	EXPORT	MAIN
;
; Exception vector table
;
	b       StartUp

	ALIGN	0x20
;----------------------------------------------------------------------
; The table of exception handlers loaded by the exception vectors above.

LoopForever
	b   LoopForever
;----------------------------------------------------------------------

; The RESET entry point
StartUp
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
;  FUNCTION:		StartUp
;
;  DESCRIPTION:		Entry point for initializing platform.
;
;  PARAMETERS:		None
;
;  RETURNS:			None
;
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    ;--------------------------------------------------------------------------
    ; MS RECOMMENDATION:
    ; Put the processor in supervisor mode
    ; Disable the interrupt request (IRQ) and fast interrupt request (FIQ)
    ; inputs
    ;--------------------------------------------------------------------------
    mrs     r0, cpsr                            ; r0 = CPSR
    mov     r0, #ARM_CPSR_MODE_SVC              ; enter supervisor mode
    orr     r0, r0, #ARM_CPSR_IRQDISABLE        ; disable normal IRQ
    orr     r0, r0, #ARM_CPSR_FIQDISABLE        ; disable fast IRQ
    msr     cpsr_c, r0                          ; update CPSR control bits

    ;--------------------------------------------------------------------------
    ; MS RECOMMENDATION:
    ; Disable memory management unit (MMU) and both the instruction and data
    ; caches
    ;--------------------------------------------------------------------------
    mrc     p15, 0, r0, c1, c0, 0               ; r0 = system control reg
    bic     r0, r0, #ARM_CTRL_ICACHE            ; disable ICache
    bic     r0, r0, #ARM_CTRL_DCACHE            ; disable DCache
    bic     r0, r0, #ARM_CTRL_MMU               ; disable MMU
    bic     r0, r0, #ARM_CTRL_VECTORS           ; set vector base to 0x00000000
    mcr     p15, 0, r0, c1, c0, 0               ; update system control reg

    ;
    ; Configure ARM Peripheral Port Memory Remap Register (PPMRR)
    ;
    ldr     r0, =ARM_PPMRR_CONFIG               ; r0 = PPMRR configuration
    mcr     p15, 0, r0, c15, c2, 4              ; update PPMRR

    ;
    ; Configure ARM coprocessor access control register
    ;
    ldr     r0, =ARM_CACR_CONFIG                ; r0 = CACR configuration
    ;mcr     p15, 0, r0, c1, c0, 2               ; update CACR

    ;
    ; configure AHB<->IP-bus interface (AIPS) registers
    ;
    ldr     r1, =CSP_BASE_REG_PA_AIPSAREG
    ldr     r2, =CSP_BASE_REG_PA_AIPSBREG

    ; except for AIPS regs, configure all peripherals as follows:
    ;   unbuffered writes (BW=0)
    ;   disable supervisor protect (SP=0)
    ;   disable write protect (WP=0)
    ;   disable trusted protect (TP=0)
    mov     r0, #0
    str     r0, [r1, #AIPSREG_PACR1_OFFSET]
    str     r0, [r1, #AIPSREG_PACR2_OFFSET]
    str     r0, [r1, #AIPSREG_PACR3_OFFSET]
    str     r0, [r1, #AIPSREG_OPACR0_OFFSET]
    str     r0, [r1, #AIPSREG_OPACR1_OFFSET]
    str     r0, [r1, #AIPSREG_OPACR2_OFFSET]
    str     r0, [r1, #AIPSREG_OPACR3_OFFSET]
    str     r0, [r1, #AIPSREG_OPACR4_OFFSET]
    str     r0, [r2, #AIPSREG_PACR1_OFFSET]
    str     r0, [r2, #AIPSREG_PACR2_OFFSET]
    str     r0, [r2, #AIPSREG_PACR3_OFFSET]
    str     r0, [r2, #AIPSREG_OPACR0_OFFSET]
    str     r0, [r2, #AIPSREG_OPACR1_OFFSET]
    str     r0, [r2, #AIPSREG_OPACR2_OFFSET]
    str     r0, [r2, #AIPSREG_OPACR3_OFFSET]
    str     r0, [r2, #AIPSREG_OPACR4_OFFSET]

    ; AIPS regs (PACR0) are configured as follows:
    ;   unbuffered writes (BW=0)
    ;   enable supervisor protect (SP=1)
    ;   disable write protect (WP=0)
    ;   disable trusted protect (TP=0)
    orr     r0, r0, #(1 << (28+2))
    str     r0, [r1, #AIPSREG_PACR0_OFFSET]
    str     r0, [r2, #AIPSREG_PACR0_OFFSET]

    ;
    ; set up system clocks
    ;

    ;!!!!! TODO: complete system clock configuration


    ;
    ; configure AHB crossbar switch (MAX) registers
    ;

    ;!!!!! TODO: MAX not in first Virtio release, skip it for now


    ;
    ; configure multi-master memory interface (M3IF) registers
    ;

    ;
    ; configure enhanced SDRAM/DDR contoller (ESDCTL) registers
    ;


    ;--------------------------------------------------------------------------
    ; MS RECOMMENDATION:
    ; Configure the interrupt controller. Mask and clear any pending
    ; interrupts.
    ;--------------------------------------------------------------------------
    mov     r0, #0
    ldr     r1, =CSP_BASE_REG_PA_AVIC
    str     r0, [r1, #AVIC_INTENABLEH_OFFSET]   ; disable all interrupt sources
    str     r0, [r1, #AVIC_INTENABLEL_OFFSET]   ; disable all interrupt sources

    ;--------------------------------------------------------------------------
    ; MS RECOMMENDATION:
    ; Set up the power management/monitoring registers. Set conditions during
    ; sleep modes.
    ;--------------------------------------------------------------------------
	IF {FALSE}
    ; Initialize setting in the CRM COM module
    mov     r0, #CRM_COM_CSCR_INIT_VALUE1
    mov     r1, #CRM_COM_CSCR_INIT_VALUE2
    orr     r0, r0, r1
    mov     r1, #CRM_COM_CSCR_INIT_VALUE3
    orr     r0, r0, r1
    ldr     r1, =CSP_BASE_REG_PA_CRM_COM
    str     r0, [r1, #CRM_COM_CSCR_OFFSET]  ; Enable CLKMON_CKIH, AP CKOH/CKO Selected

    mov     r0, #CRM_COM_CCRCR_5_SECONDS
    str     r0, [r1, #CRM_COM_CCRCR_OFFSET] ; Set cold reset divider to 5 seconds

    ; Initialize the ADPLL and set the different frequencies
    ldr     r1, =CSP_BASE_REG_PA_ADPLL
    mov     r0, #ADPLL_INIT_OP
    str     r0, [r1, #DPLL_DP_OP_OFFSET]
    mov     r0, #ADPLL_INIT_MFD
    str     r0, [r1, #DPLL_DP_MFD_OFFSET]
    mov     r0, #ADPLL_INIT_MFN
    str     r0, [r1, #DPLL_DP_MFN_OFFSET]

    mov     r0, #ADPLL_INIT_DP_CONFIG
    str     r0, [r1, #DPLL_DP_CONFIG_OFFSET]
    mov     r0, #ADPLL_INIT_DP_TOGC
    str     r0, [r1, #DPLL_DP_TOGC_OFFSET]
    mov     r0, #ADPLL_INIT_DP_DESTAT
    str     r0, [r1, #DPLL_DP_DESTAT_OFFSET]
    mov     r0, #ADPLL_INIT_DP_CTL
    str     r0, [r1, #DPLL_DP_CTL_OFFSET]           ; Restart the ADPLL at the normal frequency

    ; Set the high frequency value of the ADPLL
    mov     r0, #ADPLL_INIT_HFS_OP
    str     r0, [r1, #DPLL_DP_HFS_OP_OFFSET]
    mov     r0, #ADPLL_INIT_HFS_MFD
    str     r0, [r1, #DPLL_DP_HFS_MFD_OFFSET]
    mov     r0, #ADPLL_INIT_HFS_MFN
    str     r0, [r1, #DPLL_DP_HFS_MFN_OFFSET]

    ; Initialize the UDPLL
    ldr     r1, =CSP_BASE_REG_PA_UDPLL
    mov     r0, #UDPLL_INIT_OP
    str     r0, [r1, #DPLL_DP_OP_OFFSET]
    mov     r0, #UDPLL_INIT_MFD
    str     r0, [r1, #DPLL_DP_MFD_OFFSET]
    mov     r0, #UDPLL_INIT_MFN
    str     r0, [r1, #DPLL_DP_MFN_OFFSET]

    mov     r0, #UDPLL_INIT_DP_CONFIG
    str     r0, [r1, #DPLL_DP_CONFIG_OFFSET]
    mov     r0, #UDPLL_INIT_DP_TOGC
    str     r0, [r1, #DPLL_DP_TOGC_OFFSET]
    mov     r0, #UDPLL_INIT_DP_DESTAT
    str     r0, [r1, #DPLL_DP_DESTAT_OFFSET]
    mov     r0, #UDPLL_INIT_DP_CTL
    str     r0, [r1, #DPLL_DP_CTL_OFFSET]           ; Restart the UDPLL at the normal frequency

    ; Set the high frequency value of the UDPLL
    mov     r0, #UDPLL_INIT_HFS_OP
    str     r0, [r1, #DPLL_DP_HFS_OP_OFFSET]
    mov     r0, #UDPLL_INIT_HFS_MFD
    str     r0, [r1, #DPLL_DP_HFS_MFD_OFFSET]
    mov     r0, #UDPLL_INIT_HFS_MFN
    str     r0, [r1, #DPLL_DP_HFS_MFN_OFFSET]
	ENDIF
	
	; Set up stack in ram
	ldr		sp, =(RamPABase+StackEndInRamOffset-4)

	IF	RELOCATE_IPL
		ldr		r0, =NANDFC_BASE
		ldr		r1, =(RamPABase + IPLRelocateRamOffset)
		ldr		r2, =(NANDFC_MAIN_RAM_BUF_TOTAL_SIZE / 16)
RelocateIPL
	    ldmia   r0!, {r3-r6}
	    stmia   r1!, {r3-r6}
		subs	r2, r2, #1
		bne		RelocateIPL
		
		adr		r0, RelocateIPLDone
		ldr		r1, =NANDFC_BASE
		sub		r0, r0, r1
		ldr		r1, =(RamPABase + IPLRelocateRamOffset)
		add		r0, r0, r1
		mov		pc, r0
RelocateIPLDone
	ENDIF

	; Load and boot SPL
	b		NandBoot

;******************************************************************************
;*
;* FUNCTION:    NandBoot
;*
;* DESCRIPTION: Nand bootstrap function. Never returns.
;*
;* PARAMETERS:  None
;*
;* RETURNS:     None
;*
;******************************************************************************
NandBoot
	ldr		r4, =(NANDFC_BASE + NANDFC_REGISTERS_OFFSET)

	; unlock ram buffers
	ldrh	r5, [r4, #NANDFC_CONFIGURATION_OFFSET]
	bic		r5, r5, #3
	orr		r5, r5, #NANDFC_BLS_UNLOCK
	strh	r5, [r4, #NANDFC_CONFIGURATION_OFFSET]