📄 registers.h
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;------------------------------------------------------------------------------
;
; Copyright (C) 2004, Motorola Inc. All Rights Reserved
;
;-----------------------------------------------------------------------------
;
; Copyright (C) 2004, Freescale Semiconductor, Inc. All Rights Reserved
; THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
; BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
; FREESCALE SEMICONDUCTOR, INC.
;
;-----------------------------------------------------------------------------
;
; File: NANDLOADER/register.h
; Purpose: Defines for CPU specific register defines.
;
; Notes:
;
; Author: Swee Yee Fonn
; Date: 03/23/2004
;
; Modifications:
; MM/DD/YYYY Initials Change description
;
IF :LNOT: :DEF: _SRC_BOOTLOADER_IPL_NANDLOADER_REGISTERS_H
_SRC_BOOTLOADER_IPL_NANDLOADER_REGISTERS_H EQU 1
INCLUDE mxarm11_base_regs.inc
INCLUDE mxarm11_base_mem.inc
INCLUDE mx31_base_regs.inc
;
; ARM constants
;
ARM_CPSR_IRQDISABLE EQU (1 << 7)
ARM_CPSR_FIQDISABLE EQU (1 << 6)
ARM_CPSR_MODE_SVC EQU 0x13
ARM_CTRL_ICACHE EQU (1 << 12)
ARM_CTRL_DCACHE EQU (1 << 2)
ARM_CTRL_MMU EQU (1 << 0)
ARM_CTRL_VECTORS EQU (1 << 13)
ARM_CACR_FULL EQU 0x3
; VFP uses coproc 10 for single-precision instructions
ARM_VFP_SP_COP EQU 10
ARM_VFP_SP_ACCESS EQU (ARM_CACR_FULL << (ARM_VFP_SP_COP*2))
; VFP uses coproc 11 for double-precision instructions
ARM_VFP_DP_COP EQU 11
ARM_VFP_DP_ACCESS EQU (ARM_CACR_FULL << (ARM_VFP_DP_COP*2))
; Configure coprocessor access control
ARM_CACR_CONFIG EQU (ARM_VFP_SP_ACCESS | ARM_VFP_DP_ACCESS)
; Peripheral Port Memory Remap Register (PPMRR)
ARM_PPMRR_SIZE_LSH EQU 0
ARM_PPMRR_SIZE_WID EQU 5
ARM_PPMRR_SIZE_256MB EQU 0x13
ARM_PPMRR_SIZE_512MB EQU 0x14
ARM_PPMRR_SIZE_1GB EQU 0x15
ARM_PPMRR_BASEADDR_LSH EQU 12
ARM_PPMRR_BASEADDR_WID EQU 20
ARM_PPMRR_SIZE EQU (ARM_PPMRR_SIZE_256MB << ARM_PPMRR_SIZE_LSH)
ARM_PPMRR_BASEADDR EQU (0x60000000)
ARM_PPMRR_CONFIG EQU (ARM_PPMRR_BASEADDR | ARM_PPMRR_SIZE)
;
; AVIC constants
;
AVIC_INTCNTL_OFFSET EQU 0x0000
AVIC_NIMASK_OFFSET EQU 0x0004
AVIC_INTENNUM_OFFSET EQU 0x0008
AVIC_INTDISNUM_OFFSET EQU 0x000C
AVIC_INTENABLEH_OFFSET EQU 0x0010
AVIC_INTENABLEL_OFFSET EQU 0x0014
AVIC_INTTYPEH_OFFSET EQU 0x0018
AVIC_INTTYPEL_OFFSET EQU 0x001C
AVIC_NIPRIORITY7_OFFSET EQU 0x0020
AVIC_NIPRIORITY6_OFFSET EQU 0x0024
AVIC_NIPRIORITY5_OFFSET EQU 0x0028
AVIC_NIPRIORITY4_OFFSET EQU 0x002C
AVIC_NIPRIORITY3_OFFSET EQU 0x0030
AVIC_NIPRIORITY2_OFFSET EQU 0x0034
AVIC_NIPRIORITY1_OFFSET EQU 0x0038
AVIC_NIPRIORITY0_OFFSET EQU 0x003C
AVIC_NIVECSR_OFFSET EQU 0x0040
AVIC_FIVECSR_OFFSET EQU 0x0044
AVIC_INTSRCH_OFFSET EQU 0x0048
AVIC_INTSRCL_OFFSET EQU 0x004C
AVIC_INTFRCH_OFFSET EQU 0x0050
AVIC_INTFRCL_OFFSET EQU 0x0054
AVIC_NIPNDH_OFFSET EQU 0x0058
AVIC_NIPNDL_OFFSET EQU 0x005C
AVIC_FIPNDH_OFFSET EQU 0x0060
AVIC_FIPNDL_OFFSET EQU 0x0064
AVIC_VECTOR_OFFSET EQU 0x0100
AVIC_INTCNTL_ABFFLAG EQU (1<<25)
AVIC_INTCNTL_ABFEN EQU (1<<24)
AVIC_INTCNTL_NIDIS EQU (1<<22)
AVIC_INTCNTL_FIDIS EQU (1<<21)
AVIC_INTCNTL_NIAD EQU (1<<20)
AVIC_INTCNTL_FIAD EQU (1<<19)
AVIC_INTCNTL_NM EQU (1<<18)
;
; RTC Constants
;
RTC_HOUR_MIN_COUNTER EQU 0x0000
RTC_SEC_COUNTER EQU 0x0004
RTC_HOUR_MIN_ALARM EQU 0x0008
RTC_SEC_ALARM EQU 0x000C
RTC_CONTROL EQU 0x0010
RTC_INT_STAT EQU 0x0014
RTC_INT_ENABLE EQU 0x0018
RTC_STOPWATCH EQU 0x001C
RTC_DAY_COUNTER EQU 0x0020
RTC_DAY_ALARM EQU 0x0024
;
; AIPS Constants
;
AIPSREG_MPR0_OFFSET EQU 0x0000
AIPSREG_MPR1_OFFSET EQU 0x0004
AIPSREG_PACR0_OFFSET EQU 0x0020
AIPSREG_PACR1_OFFSET EQU 0x0024
AIPSREG_PACR2_OFFSET EQU 0x0028
AIPSREG_PACR3_OFFSET EQU 0x002C
AIPSREG_OPACR0_OFFSET EQU 0x0040
AIPSREG_OPACR1_OFFSET EQU 0x0044
AIPSREG_OPACR2_OFFSET EQU 0x0048
AIPSREG_OPACR3_OFFSET EQU 0x004C
AIPSREG_OPACR4_OFFSET EQU 0x0050
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; NANDFC registers
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; NANDFC defines
NANDFC_MAIN_BUF_SIZE EQU 512
NANDFC_SPARE_BUF_SIZE EQU 16
NANDFC_BASE EQU CSP_BASE_REG_PA_NANDFC
NANDFC_MAIN_RAM_BUF1_OFFSET EQU (NANDFC_MAIN_BUF_SIZE)
NANDFC_MAIN_RAM_BUF2_OFFSET EQU (NANDFC_MAIN_RAM_BUF1_OFFSET + NANDFC_MAIN_BUF_SIZE)
NANDFC_MAIN_RAM_BUF3_OFFSET EQU (NANDFC_MAIN_RAM_BUF2_OFFSET + NANDFC_MAIN_BUF_SIZE)
NANDFC_SPARE_RAM_BUF0_OFFSET EQU (NANDFC_MAIN_RAM_BUF3_OFFSET + NANDFC_MAIN_BUF_SIZE)
NANDFC_SPARE_RAM_BUF1_OFFSET EQU (NANDFC_SPARE_RAM_BUF0_OFFSET + NANDFC_SPARE_BUF_SIZE)
NANDFC_SPARE_RAM_BUF2_OFFSET EQU (NANDFC_SPARE_RAM_BUF1_OFFSET + NANDFC_SPARE_BUF_SIZE)
NANDFC_SPARE_RAM_BUF3_OFFSET EQU (NANDFC_SPARE_RAM_BUF2_OFFSET + NANDFC_SPARE_BUF_SIZE)
NANDFC_MAIN_RAM_BUF_TOTAL_SIZE EQU (4 * NANDFC_MAIN_BUF_SIZE)
NANDFC_REGISTERS_OFFSET EQU 0x00000E00
NANDFC_BUFSIZE_OFFSET EQU 0x00
NANDFC_RESERVED_OFFSET EQU 0x02
NANDFC_RAM_BUFF_ADD_OFFSET EQU 0x04
NANDFC_FLASH_ADD_OFFSET EQU 0x06
NANDFC_FLASH_CMD_OFFSET EQU 0x08
NANDFC_CONFIGURATION_OFFSET EQU 0x0A
NANDFC_ECC_STATUS_RESULT_OFFSET EQU 0x0C
NANDFC_ECC_STATUS_MAIN_OFFSET EQU 0x0E
NANDFC_ECC_STATUS_SPARE_OFFSET EQU 0x10
NANDFC_WRITE_PROT_OFFSET EQU 0x12
NANDFC_UNLOCK_START_BLK_OFFSET EQU 0x14
NANDFC_UNLOCK_END_BLK_OFFSET EQU 0x16
NANDFC_WRITE_PROT_STAUS_OFFSET EQU 0x18
NANDFC_CONFIG1_OFFSET EQU 0x1A
NANDFC_CONFIG2_OFFSET EQU 0x1C
; Register masks
; Configuration masks
NANDFC_BLS_UNLOCK EQU 0x0002
; ECC status register masks
NANDFC_ECC_ERM_NO_ERR EQU 0x0000
NANDFC_ECC_ERM_1BIT_ERR EQU 0x0001
NANDFC_ECC_ERM_UNRECV_ERR EQU 0x0002
NANDFC_ECC_ERM_RESERVED EQU 0x0003
; Config1 masks
NANDFC_CONFIG1_SP_EN EQU 0x0004
NANDFC_CONFIG1_ECC_EN EQU 0x0008
NANDFC_CONFIG1_INT_MSK EQU 0x0010
NANDFC_CONFIG1_DMA_REQ EQU 0x0020
; Config2 masks
NANDFC_CONFIG2_INT EQU 0x8000
NANDFC_FDO_PAGE_READ EQU 0x0008
NANDFC_FADD_ADDR_WRITE EQU 0x0002
NANDFC_FCMD_CMD_WRITE EQU 0x0001
; NANDFC buffer to use
NAND_BUFFER_IN_USE_ID EQU 0x03
NANDFC_MAIN_BUFFER_IN_USE_ADDR EQU (NANDFC_BASE + NANDFC_MAIN_RAM_BUF3_OFFSET)
NANDFC_SPARE_BUFFER_IN_USE_ADDR EQU (NANDFC_BASE + NANDFC_SPARE_RAM_BUF3_OFFSET)
ENDIF
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