📄 pbc.h
字号:
//------------------------------------------------------------------------------
//
// Copyright (C) 2004, Motorola Inc. All Rights Reserved
//
//------------------------------------------------------------------------------
//
// Copyright (C) 2004, Freescale Semiconductor, Inc. All Rights Reserved
// THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
// BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
// FREESCALE SEMICONDUCTOR, INC.
//
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Header: pbc.h
//
// Provides definitions for the Peripheral Bus Control (PBC) module of the
// EVB main board. The PBC is implented using a CPLD.
//
//------------------------------------------------------------------------------
#ifndef __PBC_H
#define __PBC_H
#if __cplusplus
extern "C" {
#endif
//------------------------------------------------------------------------------
// GENERAL MODULE CONSTANTS
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// REGISTER LAYOUT
//------------------------------------------------------------------------------
typedef struct
{
UINT16 VERSION;
UINT16 BSTAT2;
UINT16 BCTRL1_SET;
UINT16 BCTRL1_CLEAR;
UINT16 BCTRL2_SET;
UINT16 BCTRL2_CLEAR;
UINT16 BCTRL3_SET;
UINT16 BCTRL3_CLEAR;
UINT16 BCTRL4_SET;
UINT16 BCTRL4_CLEAR;
UINT16 BSTAT1;
UINT16 INT_STATUS;
UINT16 INT_CUR_STATUS;
UINT16 INT_MASK_SET;
UINT16 INT_MASK_CLEAR;
} CSP_PBC_REGS, *PCSP_PBC_REGS;
//------------------------------------------------------------------------------
// REGISTER OFFSETS
//------------------------------------------------------------------------------
#define PBC_SC16C652_BASE_OFFSET 0x00010000
#define PBC_SC16C652_PORTA_OFFSET 0x00010000
#define PBC_SC16C652_PORTB_OFFSET 0x00010010
#define PBC_CS8900_BASE_OFFSET 0x00020000
#define PBC_CS8900_IOBASE_OFFSET 0x00020000
#define PBC_CS8900_MEMBASE_OFFSET 0x00021000
#define PBC_CS8900_DMABASE_OFFSET 0x00022000
#define PBC_XCS0_OFFSET 0x00040000
#define PBC_XCS1_OFFSET 0x00050000
#define PBC_LCD_EN_B_OFFSET 0x00060000
#define PBC_CODE_B_OFFSET 0x00070000
// PBC Registers
#define PBC_VERSION_OFFSET 0x0
#define PBC_BSTAT_OFFSET 0x2
#define PBC_BCTRL1_SET_OFFSET 0x4
#define PBC_BCTRL1_CLEAR_OFFSET 0x6
#define PBC_BCTRL2_SET_OFFSET 0x8
#define PBC_BCTRL2_CLEAR_OFFSET 0xA
//------------------------------------------------------------------------------
// REGISTER BIT FIELD POSITIONS (LEFT SHIFT)
//------------------------------------------------------------------------------
#define PBC_VERSION_BASE_LSH 0
#define PBC_VERSION_CPU_LSH 4
#define PBC_VERSION_PBC_LSH 8
#define PBC_BSTAT2_DSW_LSH 0
#define PBC_BSTAT2_DMA_REQ_LSH 8
#define PBC_BCTRL1_SET_ERST_LSH 0
#define PBC_BCTRL1_SET_URST_LSH 1
#define PBC_BCTRL1_SET_UENA_LSH 2
#define PBC_BCTRL1_SET_UENB_LSH 3
#define PBC_BCTRL1_SET_UENCE_LSH 4
#define PBC_BCTRL1_SET_IREN_LSH 5
#define PBC_BCTRL1_SET_LED0_LSH 6
#define PBC_BCTRL1_SET_LED1_LSH 7
#define PBC_BCTRL1_SET_CCTL_LSH 8
#define PBC_BCTRL1_SET_SIMP_LSH 11
#define PBC_BCTRL1_SET_MCP1_LSH 12
#define PBC_BCTRL1_SET_MCP2_LSH 13
#define PBC_BCTRL1_SET_BEND_LSH 14
#define PBC_BCTRL1_SET_LCDON_LSH 15
#define PBC_BCTRL1_CLEAR_ERST_LSH 0
#define PBC_BCTRL1_CLEAR_URST_LSH 1
#define PBC_BCTRL1_CLEAR_UENA_LSH 2
#define PBC_BCTRL1_CLEAR_UENB_LSH 3
#define PBC_BCTRL1_CLEAR_UENCE_LSH 4
#define PBC_BCTRL1_CLEAR_IREN_LSH 5
#define PBC_BCTRL1_CLEAR_LED0_LSH 6
#define PBC_BCTRL1_CLEAR_LED1_LSH 7
#define PBC_BCTRL1_CLEAR_CCTL_LSH 8
#define PBC_BCTRL1_CLEAR_SIMP_LSH 11
#define PBC_BCTRL1_CLEAR_MCP1_LSH 12
#define PBC_BCTRL1_CLEAR_MCP2_LSH 13
#define PBC_BCTRL1_CLEAR_BEND_LSH 14
#define PBC_BCTRL1_CLEAR_LCDON_LSH 15
#define PBC_BCTRL2_USELA_LSH 0
#define PBC_BCTRL2_USELB_LSH 1
#define PBC_BCTRL2_USELC_LSH 2
#define PBC_BCTRL2_UMODENA_LSH 3
#define PBC_BCTRL2_UMODENC_LSH 4
#define PBC_BCTRL2_CSI_EN_LSH 5
#define PBC_BCTRL2_ATA_EN_LSH 6
#define PBC_BCTRL2_ATA_SEL_LSH 7
#define PBC_BCTRL2_IRDA_MOD_LSH 8
#define PBC_BCTRL2_LCDRST0_LSH 9
#define PBC_BCTRL2_LCDRST1_LSH 10
#define PBC_BCTRL2_LCDRST2_LSH 11
#define PBC_BCTRL2_LCDIO_EN_LSH 12
#define PBC_BCTRL2_CT_CS_LSH 13
#define PBC_BCTRL2_VPPEN_LSH 14
#define PBC_BCTRL2_VCCEN_LSH 15
#define PBC_STAT1_NF_DET_LSH 0
#define PBC_STAT1_KP_ON_LSH 1
#define PBC_STAT1_LIGHT_SENSE_LSH 2
#define PBC_STAT1_ATA_IOCS16_LSH 3
#define PBC_STAT1_ATA_CBLID_LSH 4
#define PBC_STAT1_ATA_DASP_LSH 5
#define PBC_STAT1_PWR_RDY_LSH 6
#define PBC_STAT1_SD1_WP_LSH 7
#define PBC_STAT1_SD2_WP_LSH 8
#define PBC_STAT1_FLIP_SENSE1_LSH 9
#define PBC_STAT1_FLIP_SENSE2_LSH 10
#define PBC_STAT1_PTT_LSH 11
#define PBC_STAT1_MC13783_IN_LSH 12
#define PBC_INT_LOW_BAT_LSH 0
#define PBC_INT_PB_IRQ_LSH 1
#define PBC_INT_OTG_FS_OVR_LSH 2
#define PBC_INT_FSH_OVR_LSH 3
#define PBC_INT_ENET_LSH 8
#define PBC_INT_OTG_FS_LSH 9
#define PBC_INT_XUART_INTA_LSH 10
#define PBC_INT_XUART_INTB_LSH 11
#define PBC_INT_SYNTH_LSH 12
#define PBC_INT_CE_INT1_LSH 13
#define PBC_INT_CE_INT2_LSH 14
//------------------------------------------------------------------------------
// REGISTER BIT FIELD WIDTHS
//------------------------------------------------------------------------------
#define PBC_VERSION_BASE_WID 4
#define PBC_VERSION_CPU_WID 4
#define PBC_VERSION_PBC_WID 8
#define PBC_BSTAT2_DSW_WID 8
#define PBC_BSTAT2_DMA_REQ_WID 1
#define PBC_BCTRL1_SET_ERST_WID 1
#define PBC_BCTRL1_SET_URST_WID 1
#define PBC_BCTRL1_SET_UENA_WID 1
#define PBC_BCTRL1_SET_UENB_WID 1
#define PBC_BCTRL1_SET_UENCE_WID 1
#define PBC_BCTRL1_SET_IREN_WID 1
#define PBC_BCTRL1_SET_LED0_WID 1
#define PBC_BCTRL1_SET_LED1_WID 1
#define PBC_BCTRL1_SET_CCTL_WID 3
#define PBC_BCTRL1_SET_SIMP_WID 1
#define PBC_BCTRL1_SET_MCP1_WID 1
#define PBC_BCTRL1_SET_MCP2_WID 1
#define PBC_BCTRL1_SET_BEND_WID 1
#define PBC_BCTRL1_SET_LCDON_WID 1
#define PBC_BCTRL1_CLEAR_ERST_WID 1
#define PBC_BCTRL1_CLEAR_URST_WID 1
#define PBC_BCTRL1_CLEAR_UENA_WID 1
#define PBC_BCTRL1_CLEAR_UENB_WID 1
#define PBC_BCTRL1_CLEAR_UENCE_WID 1
#define PBC_BCTRL1_CLEAR_IREN_WID 1
#define PBC_BCTRL1_CLEAR_LED0_WID 1
#define PBC_BCTRL1_CLEAR_LED1_WID 1
#define PBC_BCTRL1_CLEAR_CCTL_WID 3
#define PBC_BCTRL1_CLEAR_SIMP_WID 1
#define PBC_BCTRL1_CLEAR_MCP1_WID 1
#define PBC_BCTRL1_CLEAR_MCP2_WID 1
#define PBC_BCTRL1_CLEAR_BEND_WID 1
#define PBC_BCTRL1_CLEAR_LCDON_WID 1
#define PBC_BCTRL2_USELA_WID 1
#define PBC_BCTRL2_USELB_WID 1
#define PBC_BCTRL2_USELC_WID 1
#define PBC_BCTRL2_UMODENA_WID 1
#define PBC_BCTRL2_UMODENC_WID 1
#define PBC_BCTRL2_CSI_EN_WID 1
#define PBC_BCTRL2_ATA_EN_WID 1
#define PBC_BCTRL2_ATA_SEL_WID 1
#define PBC_BCTRL2_IRDA_MOD_WID 1
#define PBC_BCTRL2_LCDRST0_WID 1
#define PBC_BCTRL2_LCDRST1_WID 1
#define PBC_BCTRL2_LCDRST2_WID 1
#define PBC_BCTRL2_LCDIO_EN_WID 1
#define PBC_BCTRL2_CT_CS_WID 1
#define PBC_BCTRL2_VPPEN_WID 1
#define PBC_BCTRL2_VCCEN_WID 1
#define PBC_BCTRL3_OTG_FS_SEL 0 // 0 = the source is the MC13783 board.
// 1 = the source is the CPU.
#define PBC_BCTRL3_OTG_FS_EN 1 // 0 = OTG Full Speed Interface enabled
// 1 = OTG Full Speed Interface disabled
#define PBC_BCTRL3_FSH_SEL 2 // 0 = Group A on the CPU
// 1 =Group B on the CPU
#define PBC_BCTRL3_FSH_EN 3 // 0 = Full Speed Host Interface enabled
// 1 = Full Speed Host Interface disabled
#define PBC_BCTRL3_HSH_SEL 4 // 0 = Group A on the CPU
// 1 =Group B on the CPU
#define PBC_BCTRL3_HSH_EN 5 // 0 = High Speed Host Interface enabled
// 1 = High Speed Host Interface disabled
#define PBC_BCTRL3_FSH_MODE 6 // 0 = Single ended mode
// 1 = Differential mode
#define PBC_BCTRL3_OTG_HS_EN 7 // 0 = OTG High Speed Interface enabled
// 1 = OTG High Speed Interface disabled
#define PBC_BCTRL3_OTG_VBUS_EN 8 // 0 = OTG VBUS regulator is enabled
// 1 = OTG VBUS regulator is disabled
#define PBC_BCTRL3_FSH_VBUS_EN 9 // 0 = Full Speed Host VBUS regulator is enabled
// 1 = Full Speed Host VBUS regulator is disabled
#define PBC_BCTRL3_CARD1_SEL 10 // 0 = lines are dedicated to SD1 interface
// 1 = lines are dedicated to MS1 interface
#define PBC_BCTRL3_CARD2_SEL 11 // 0 = lines are dedicated to PCMCIA &SD2 interface
// 1 = lines are dedicated to MS2 interface
#define PBC_BCTRL3_SYNTH_RST 12 // 0= Reset audio Synthesizer
// 1= Normal operation
#define PBC_BCTRL3_VSIM_EN 13 // 0 = VSIM regulator is disabled
// 1 = VSIM regulator is enabled
#define PBC_BCTRL3_VESIM_EN 14 // 0 = VESIM regulator is disabled
// 1 = VESIM regulator is enabled
#define PBC_BCTRL3_SPI3_RESET 15 // 0 = CSPI3 is reset
// 1 = Normal operation
#define PBC_STAT1_NF_DET_WID 1
#define PBC_STAT1_KP_ON_WID 1
#define PBC_STAT1_LIGHT_SENSE_WID 1
#define PBC_STAT1_ATA_IOCS16_WID 1
#define PBC_STAT1_ATA_CBLID_WID 1
#define PBC_STAT1_ATA_DASP_WID 1
#define PBC_STAT1_PWR_RDY_WID 1
#define PBC_STAT1_SD1_WP_WID 1
#define PBC_STAT1_SD2_WP_WID 1
#define PBC_STAT1_FLIP_SENSE1_WID 1
#define PBC_STAT1_FLIP_SENSE2_WID 1
#define PBC_STAT1_PTT_WID 1
#define PBC_STAT1_MC13783_IN_WID 1
#define PBC_INT_LOW_BAT_WID 1
#define PBC_INT_PB_IRQ_WID 1
#define PBC_INT_OTG_FS_OVR_WID 1
#define PBC_INT_FSH_OVR_WID 1
#define PBC_INT_ENET_WID 1
#define PBC_INT_OTG_FS_WID 1
#define PBC_INT_XUART_INTA_WID 1
#define PBC_INT_XUART_INTB_WID 1
#define PBC_INT_SYNTH_WID 1
#define PBC_INT_CE_INT1_WID 1
#define PBC_INT_CE_INT2_WID 1
//------------------------------------------------------------------------------
// REGISTER BIT WRITE VALUES
//------------------------------------------------------------------------------
#define PBC_BSTAT_CPUT_ZEUS 0
#define PBC_BSTAT_CPUT_SCM 1
#define PBC_BSTAT_CPUT_ARGON 2
#define PBC_BSTAT_CPUT_RESERVED 3
//------------------------------------------------------------------------------
// FUNCTION PROTOTYPES
//------------------------------------------------------------------------------
#ifdef __cplusplus
}
#endif
#endif // __PBC_H
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -