oemaddrtab_cfg.inc

freescale i.mx31 BSP CE5.0全部源码

;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
;------------------------------------------------------------------------------
;
; Copyright (C) 2004, Freescale Semiconductor, Inc. All Rights Reserved
; THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
; BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
; FREESCALE SEMICONDUCTOR, INC.
;
;------------------------------------------------------------------------------
;
;  File:  oemaddrtab_cfg.inc
;
;  This file is used to define g_oalAddressTable. This table is passed to
;  KernelStart to estabilish physical to virtual memory mapping. This table
;  is used also in IOMEM OAL module to map between physical and virtual
;  memory addresses via OALPAtoVA/OALVAtoPA functions.
;
;------------------------------------------------------------------------------

; Export Definition

        EXPORT  g_oalAddressTable[DATA]

;------------------------------------------------------------------------------
;
; TABLE FORMAT
;       cached address, physical address, size
;------------------------------------------------------------------------------

g_oalAddressTable

    DCD 0x88000000, CSP_BASE_MEM_PA_CSD0, 128           ; RAM image mapping
    DCD 0x80000000, CSP_BASE_MEM_PA_CS0, 64             ; FLASH image mapping
    DCD 0x90000000, CSP_BASE_MEM_PA_CS4, 32             ; External WEIM CS4
    DCD 0x97000000, CSP_BASE_REG_PA_AVIC, 1             ; AVIC regs
    DCD 0x97200000, CSP_BASE_REG_PA_NANDFC, 1           ; NANDFC regs
    DCD 0x97300000, CSP_BASE_REG_PA_WEIM, 1             ; WEIM regs
    DCD 0x97400000, CSP_BASE_REG_PA_M3IF, 1             ; M3IF regs
    DCD 0x97500000, CSP_BASE_REG_PA_ESDCTL, 1           ; ESDCTL regs
    DCD 0x97600000, CSP_BASE_REG_PA_L2CC, 1             ; L2CC controller regs
    DCD 0x98000000, CSP_BASE_MEM_PA_AIPSA, 64           ; AIPSA peripheral regs
    DCD 0x9C000000, CSP_BASE_MEM_PA_AIPSB, 64           ; AIPSB peripheral regs
    DCD 0x00000000, 0x00000000, 0                       ; Terminate table

;------------------------------------------------------------------------------

        END