📄 startup.s
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ldr r0, =0xD0D0
strh r0, [r2]
; Write flash config register
ldr r0, =0x56CA
strh r0, [r2]
; Flash reset command
ldr r0, =0xF0F0
strh r0, [r1]
ldr r1, =CSP_BASE_REG_PA_WEIM
; CS0 control (upper)
; EDC - 3 extra dead cycles (3 << 0) = 0x00000003
; WWS - 0 extra write wait states (0 << 4) = 0x00000000
; EW - Posedge DTACK (0 << 7) = 0x00000000
; WSC - 12 wait states (12 << 8) = 0x00000C00
; CNC - 3 CS negation cycles (3 << 14) = 0x0000C000
; DOL - 0 clock burst latency (0 << 16) = 0x00000000
; SYNC - Disable sync burst (0 << 20) = 0x00000000
; PME - Disable page mode (0 << 21) = 0x00000000
; PSZ - 4 word burst/page (0 << 22) = 0x00000000
; BCS - 1 BCLK delay (0 << 24) = 0x00000000
; BCD - /1 burst clock (0 << 28) = 0x00000000
; WP - No write protect (0 << 30) = 0x00000000
; SP - All user mode access (0 << 31) = 0x00000000
; ------------
; 0x0000CC03
;ldr r0, =0x0000CC03
ldr r0, =0x23524E80
str r0, [r1, #WEIM_CSCR0U_OFFSET]
; CS0 control (lower)
; CSEN - Enable chip select (1 << 0) = 0x00000001
; WRAP - No wrap (0 << 1) = 0x00000000
; CRE - CRE pin 0 (0 << 2) = 0x00000000
; PSR - PSRAM mode disabled (0 << 3) = 0x00000000
; CSN - 2 AHB clocks (2 << 4) = 0x00000000
; DSZ - 16-bit DATA[15:0] (5 << 8) = 0x00000500
; EBC - Only write asserts EB (1 << 11) = 0x00000800
; CSA - 2 half AHB clocks (0 << 12) = 0x00000000
; EBWN - 3 half AHB clocks (3 << 16) = 0x00030000
; EBWA - 3 half AHB clocks (3 << 20) = 0x00300000
; OEN - 2 half AHB clocks (0 << 24) = 0x00000000
; OEA - 10 half AHB clocks (10 << 28) = 0xA0000000
; ------------
; 0xA0330D01
;ldr r0, =0xA0330D01
ldr r0, =0x10000D03
str r0, [r1, #WEIM_CSCR0L_OFFSET]
; CS0 control (additional)
; FCE - Data capture by AHB clk (0 << 0) = 0x00000000
; CNC2 - No CNC increase (0 << 1) = 0x00000000
; AGE - Disable ack glue logic (0 << 2) = 0x00000000
; WWU - Forbit wrap on write (0 << 3) = 0x00000000
; DCT - 2 AHB clocks (0 << 4) = 0x00000000
; DWW - wait states same as read (0 << 6) = 0x00000000
; LBA - 0 half AHB clock (0 << 8) = 0x00000000
; LBN - 2 half AHB clocks (2 << 10) = 0x00000800
; LAH - 3 half AHB clocks (2 << 13) = 0x00000000
; MUM - Non-muxed mode (0 << 14) = 0x00000000
; RWN - 2 half AHB clocks (2 << 16) = 0x00020000
; RWA - 2 half AHB clocks (2 << 20) = 0x00200000
; EBRN - 0 half AHB clocks (0 << 24) = 0x00000000
; EBRA - 0 half AHB clocks (0 << 28) = 0x00000000
; ------------
; 0x00220800
;ldr r0, =0x00220800
ldr r0, =0x00720900
str r0, [r1, #WEIM_CSCR0A_OFFSET]
; Only configure ESDCTL if we are not currently running from SDRAM
ldr r1, =CSP_BASE_MEM_PA_CSD0
cmp pc, r1
blt esdctl_init ; if (pc < CSP_BASE_MEM_PA_CSD0) goto esdctl_init
ldr r1, =CSP_BASE_MEM_PA_CS0
cmp pc, r1
blt cache_init ; if (pc < CSP_BASE_MEM_PA_CS0) goto cache init
esdctl_init
;
; Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
; in SW_PAD_CTL registers
;
; SDCLK
ldr r1, =(CSP_BASE_REG_PA_IOMUXC+0x26C)
ldr r0, [r1]
bic r0, r0, #(1 << 12)
str r0, [r1]
; CAS
ldr r1, =(CSP_BASE_REG_PA_IOMUXC+0x270)
ldr r0, [r1]
bic r0, r0, #(1 << 22)
str r0, [r1]
; RAS
ldr r1, =(CSP_BASE_REG_PA_IOMUXC+0x274)
ldr r0, [r1]
bic r0, r0, #(1 << 2)
str r0, [r1]
; CS2 (CSD0)
ldr r1, =(CSP_BASE_REG_PA_IOMUXC+0x27C)
ldr r0, [r1]
bic r0, r0, #(1 << 22)
str r0, [r1]
; DQM3
ldr r1, =(CSP_BASE_REG_PA_IOMUXC+0x284)
ldr r0, [r1]
bic r0, r0, #(1 << 22)
str r0, [r1]
; DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
ldr r1, =(CSP_BASE_REG_PA_IOMUXC+0x288)
ldr r2, =22 ; (0x2E0 - 0x288) / 4 = 22
pad_loop
ldr r0, [r1]
bic r0, r0, #(1 << 22)
bic r0, r0, #(1 << 12)
bic r0, r0, #(1 << 2)
str r0, [r1]
add r1, r1, #4
subs r2, r2, #0x1
bne pad_loop
;
; Configure enhanced SDRAM/DDR contoller (ESDCTL)
;
ldr r1, =CSP_BASE_REG_PA_ESDCTL
ldr r2, =CSP_BASE_MEM_PA_CSD0
; Configure SDRAM timing parameters
ldr r0, =0x006AC73A
str r0, [r1, #ESDCTL_ESDCFG0_OFFSET]
; Reset
ldr r0, =0x2
str r0, [r1, #ESDCTL_ESDMISC_OFFSET]
; Configure for DDR
ldr r0, =0x4
str r0, [r1, #ESDCTL_ESDMISC_OFFSET]
; Hold for more than 200ns
ldr r0, =0x10000
hold
subs r0, r0, #0x1
bne hold
; Set precharge command
;
; COL - 9 column addresses (1 << 20) = 0x00100000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Precharge command (1 << 28) = 0x10000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0x92100000
ldr r0, =0x92100000
str r0, [r1, #ESDCTL_ESDCTL0_OFFSET]
; Access SDRAM with A10 high to precharge all banks
ldr r0, =0x0
str r0, [r2, #0xF00]
; Set autorefresh command
;
; COL - 9 column addresses (1 << 20) = 0x00100000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Autorefresh command (2 << 28) = 0x20000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0xA2100000
ldr r0, =0xA2100000
str r0, [r1, #ESDCTL_ESDCTL0_OFFSET]
; Use writes to refresh all banks of SDRAM
ldr r0, =0x0
str r0, [r2]
str r0, [r2]
; Set load mode command
;
; COL - 9 column addresses (1 << 20) = 0x00100000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Load mode command (3 << 28) = 0x30000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0xB2100000
ldr r0, =0xB2100000
str r0, [r1, #ESDCTL_ESDCTL0_OFFSET]
; Use SDRAM write to load SDRAM mode register
ldr r0, =0x0
strb r0, [r2, #0x33] ; address used for mode, data ignored
ldr r3, =(CSP_BASE_MEM_PA_CSD0+0x01000000)
strb r0, [r3] ; address used for mode, data ignored
; Set load mode command
;
; PRCT - Precharge timer disabled (0 << 0) = 0x00000000
; BL - Burst of 8 for SDR/DDR (1 << 7) = 0x00000080
; FP - No full page mode (0 << 8) = 0x00000000
; PWDT - Power down timeout 128 clocks (3 << 10) = 0x00000C00
; SREFR - 4 rows refreshed each clock (3 << 13) = 0x00006000
; DSIZ - 32-bit memory width (2 << 16) = 0x00020000
; COL - 10 column addresses (2 << 20) = 0x00200000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Normal mode command (0 << 28) = 0x00000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0x82226C80
ldr r0, =0x82226C80
str r0, [r1, #ESDCTL_ESDCTL0_OFFSET]
; Configure misc SDRAM parameters
ldr r0, =0xC
str r0, [r1, #ESDCTL_ESDMISC_OFFSET]
; Increase hold time on DDR write delay lines
; ldr r0, =0x60000
; str r0, [r1, #ESDCTL_ESDDLY5_OFFSET]
cache_init
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Flush or invalidate the instruction and data caches and the translation
; look-aside buffer (TLB) and empty the write buffers
;--------------------------------------------------------------------------
bl OALClearUTLB
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 ; flush the unified cache
IF :LNOT: BOOTLOADER
; Read PBC user switches to L2 configuration
ldr r5, =CSP_BASE_MEM_PA_CS4
ldrh r5, [r5, #PBC_BSTAT2_OFFSET]
; Check if we want to keep L2 disabled
ands r0, r5, #BSP_PBC_DSW_L2
bne AVIC_CONFIG
ldr r1, =CSP_BASE_REG_PA_L2CC
L2_532
;
; Configure L2 cache attributes
;
; L2 Auxiliary Control Register (AUXCR)
; Data RAM Read = 5 cycle latency = (4 << 0) = 0x00000004
; Data RAM Write = 5 cycle latency = (4 << 3) = 0x00000020
; Associativity = 8-way = (8 << 13) = 0x00010000
; Way Size = 16 KB = (1 << 17) = 0x00020000
; ------------
; 0x00030024
ldr r0, =0x00030024
str r0, [r1, #L2CC_AUXCR_OFFSET]
L2_INVALIDATE
;
; Invalidate L2 cache memory
;
;
ldr r0, =0x000000FF
str r0, [r1, #L2CC_INVWAY_OFFSET]
;
; Wait for invalidation to complete
;
L2_LOOP
ldr r0, [r1, #L2CC_INVWAY_OFFSET]
cmp r0, #0
bne L2_LOOP
;
; Force L2 write-through (ARM L2CC errata prevents using write-back)
;
; L2 Debug Control Register (DBGCR)
; DCL = Enable cache line fills = (0 << 0) = 0x00000000
; DWB = Disable write-back = (1 << 1) = 0x00000002
; ------------
; 0x00000002
ldr r0, =0x00000002
str r0, [r1, #L2CC_DBGCR_OFFSET]
;
; Enable L2 cache
;
ldr r0, =0x1
str r0, [r1, #L2CC_CR_OFFSET]
ENDIF
AVIC_CONFIG
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Configure the interrupt controller. Mask and clear any pending
; interrupts.
;--------------------------------------------------------------------------
mov r0, #0
ldr r1, =CSP_BASE_REG_PA_AVIC
str r0, [r1, #AVIC_INTENABLEH_OFFSET] ; disable all interrupt sources
str r0, [r1, #AVIC_INTENABLEL_OFFSET] ; disable all interrupt sources
str r0, [r1, #AVIC_INTTYPEH_OFFSET] ; all sources generate norm IRQ
str r0, [r1, #AVIC_INTTYPEL_OFFSET] ; all sources generate norm IRQ
str r0, [r1, #AVIC_INTFRCH_OFFSET] ; no sources forced
str r0, [r1, #AVIC_INTFRCL_OFFSET] ; no sources forced
str r0, [r1, #AVIC_NIPRIORITY7_OFFSET] ; all sources lowest priority
str r0, [r1, #AVIC_NIPRIORITY6_OFFSET] ; all sources lowest priority
str r0, [r1, #AVIC_NIPRIORITY5_OFFSET] ; all sources lowest priority
str r0, [r1, #AVIC_NIPRIORITY4_OFFSET] ; all sources lowest priority
str r0, [r1, #AVIC_NIPRIORITY3_OFFSET] ; all sources lowest priority
str r0, [r1, #AVIC_NIPRIORITY2_OFFSET] ; all sources lowest priority
str r0, [r1, #AVIC_NIPRIORITY1_OFFSET] ; all sources lowest priority
str r0, [r1, #AVIC_NIPRIORITY0_OFFSET] ; all sources lowest priority
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Initialize the real-time clock count register to 0 and enable the
; real-time clock.
;--------------------------------------------------------------------------
mov r0, #0x80
ldr r1, =CSP_BASE_REG_PA_RTC
str r0, [r1, #RTC_CONTROL] ; Enable RTC, Select 32768Hz
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Set up the power management/monitoring registers. Set conditions during
; sleep modes.
;--------------------------------------------------------------------------
; Initialize setting in the CRM COM module
; Initialize the ADPLL and set the different frequencies
; Set the high frequency value of the ADPLL
; Initialize the UDPLL
; Set the high frequency value of the UDPLL
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Turn on all board-level clocks and on chip peripheral clocks.
;--------------------------------------------------------------------------
; Per PBC spec, provide transition of SBHE input after reset via
; dummy read to odd location
ldr r1, =CSP_BASE_MEM_PA_CS4
ldrb r0, [r1, #0x7]
mov r0, #(1 << 15)
strh r0, [r1, #PBC_BCTRL1_SET_OFFSET]
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Get the physical base address of the OEMAddressTable and store in r0.
;--------------------------------------------------------------------------
adr r0, g_oalAddressTable
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Jump to KernelStart to boot WindowsCE or BootloaderMain for bootloader
;--------------------------------------------------------------------------
b KernelStart
spin
b spin
; Include memory configuration file with g_oalAddressTable
INCLUDE oemaddrtab_cfg.inc
ENTRY_END StartUp
END
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