📄 s3c2410.h.svn-base
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#ifndef S3C2410_H#define S3C2410_H#include "global.h"#include "arm.h"#define S3C2410_REGBASE 0x48000000/************************************//* Memory Controller Registers *//************************************/#define BWSCON REGL(S3C2410_REGBASE, 0x00000000)#define BANKCON0 REGL(S3C2410_REGBASE, 0x00000004)#define BANKCON1 REGL(S3C2410_REGBASE, 0x00000008)#define BANKCON2 REGL(S3C2410_REGBASE, 0x0000000c)#define BANKCON3 REGL(S3C2410_REGBASE, 0x00000010)#define BANKCON4 REGL(S3C2410_REGBASE, 0x00000014)#define BANKCON5 REGL(S3C2410_REGBASE, 0x00000018)#define BANKCON6 REGL(S3C2410_REGBASE, 0x0000001c)#define BANKCON7 REGL(S3C2410_REGBASE, 0x00000020)#define REFRESH REGL(S3C2410_REGBASE, 0x00000024)#define BANKSIZE REGL(S3C2410_REGBASE, 0x00000028)#define MRSRB6 REGL(S3C2410_REGBASE, 0x0000002c)#define MRSRB7 REGL(S3C2410_REGBASE, 0x00000030)/*********************************//* Memory Types *//*********************************/#define MT_SRAM 0x0#define MT_SDRAM 0x3/*********************//* UART Registers *//*********************/#define ULCON0 REGL(S3C2410_REGBASE, 0x08000000)#define ULCON1 REGL(S3C2410_REGBASE, 0x08004000)#define ULCON2 REGL(S3C2410_REGBASE, 0x08008000)#define UCON0 REGL(S3C2410_REGBASE, 0x08000004)#define UCON1 REGL(S3C2410_REGBASE, 0x08004004)#define UCON2 REGL(S3C2410_REGBASE, 0x08008004)#define UFCON0 REGL(S3C2410_REGBASE, 0x08000008)#define UFCON1 REGL(S3C2410_REGBASE, 0x08004008)#define UFCON2 REGL(S3C2410_REGBASE, 0x08008008)#define UMCON0 REGL(S3C2410_REGBASE, 0x0800000c)#define UMCON1 REGL(S3C2410_REGBASE, 0x0800400c)#define UMCON2 REGL(S3C2410_REGBASE, 0x0800800c)#define UTRSTAT0 REGL(S3C2410_REGBASE, 0x08000010)#define UTRSTAT1 REGL(S3C2410_REGBASE, 0x08004010)#define UTRSTAT2 REGL(S3C2410_REGBASE, 0x08008010)#define UERSTAT0 REGL(S3C2410_REGBASE, 0x08000014)#define UERSTAT1 REGL(S3C2410_REGBASE, 0x08004014)#define UERSTAT2 REGL(S3C2410_REGBASE, 0x08008014)#define UFSTAT0 REGL(S3C2410_REGBASE, 0x08000018)#define UFSTAT1 REGL(S3C2410_REGBASE, 0x08004018)#define UFSTAT2 REGL(S3C2410_REGBASE, 0x08008018)#define UMSTAT0 REGL(S3C2410_REGBASE, 0x0800001c)#define UMSTAT1 REGL(S3C2410_REGBASE, 0x0800401c)#define UMSTAT2 REGL(S3C2410_REGBASE, 0x0800801c)#ifdef __BIG_ENDIAN#define UTXH0 REGB(S3C2410_REGBASE, 0x08000023)#define UTXH1 REGB(S3C2410_REGBASE, 0x08004023)#define UTXH2 REGB(S3C2410_REGBASE, 0x08008023)#define URXH0 REGB(S3C2410_REGBASE, 0x08000027)#define URXH1 REGB(S3C2410_REGBASE, 0x08004027)#define URXH2 REGB(S3C2410_REGBASE, 0x08008027)#else#define UTXH0 REGB(S3C2410_REGBASE, 0x08000020)#define UTXH1 REGB(S3C2410_REGBASE, 0x08004020)#define UTXH2 REGB(S3C2410_REGBASE, 0x08008020)#define URXH0 REGB(S3C2410_REGBASE, 0x08000024)#define URXH1 REGB(S3C2410_REGBASE, 0x08004024)#define URXH2 REGB(S3C2410_REGBASE, 0x08008024)#endif /*__BIG_ENDIAN*/#define UBRDIV0 REGL(S3C2410_REGBASE, 0x08000028)#define UBRDIV1 REGL(S3C2410_REGBASE, 0x08004028)#define UBRDIV2 REGL(S3C2410_REGBASE, 0x08008028)/*********************************//* Clock & Power Registers *//*********************************/#define LOCKTIME REGL(S3C2410_REGBASE, 0x04000000)#define MPLLCON REGL(S3C2410_REGBASE, 0x04000004)#define UPLLCON REGL(S3C2410_REGBASE, 0x04000008)#define CLKCON REGL(S3C2410_REGBASE, 0x0400000c)#define CLKSLOW REGL(S3C2410_REGBASE, 0x04000010)#define CLKDIVN REGL(S3C2410_REGBASE, 0x04000014)/**************************************//* Interrupt Controller Registers *//**************************************/#define SRCPND REGL(S3C2410_REGBASE, 0x02000000)#define INTMOD REGL(S3C2410_REGBASE, 0x02000004)#define INTMSK REGL(S3C2410_REGBASE, 0x02000008)#define PRIORITY REGL(S3C2410_REGBASE, 0x0200000c)#define INTPND REGL(S3C2410_REGBASE, 0x02000010)#define INTOFFSET REGL(S3C2410_REGBASE, 0x02000014)#define SUBSRCPND REGL(S3C2410_REGBASE, 0x02000018)#define INTSUBMSK REGL(S3C2410_REGBASE, 0x0200001c)/**************************************//* Interrupt sources *//**************************************/#define INT_ADC 31#define INT_RTC 30#define INT_SPI1 29#define INT_UART0 28#define INT_IIC 27#define INT_USBH 26#define INT_USBD 25/*Reserved 24*/#define INT_UART1 23#define INT_SPI0 22#define INT_SDI 21#define INT_DMA3 20#define INT_DMA2 19#define INT_DMA1 18#define INT_DMA0 17#define INT_LCD 16#define INT_UART2 15#define INT_TIMER4 14#define INT_TIMER3 13#define INT_TIMER2 12#define INT_TIMER1 11#define INT_TIMER0 10#define INT_WDT 9#define INT_TICK 8#define nBATT_FLT 7/*Reserved 6*/#define EINT8_23 5#define EINT4_7 4#define EINT3 3#define EINT2 2#define EINT1 1#define EINT0 0/*********************************//* WatchDog Timers Registers *//*********************************/#define WTCON REGL(S3C2410_REGBASE, 0x0b000000)#define WTDAT REGL(S3C2410_REGBASE, 0x0b000004)#define WTCNT REGL(S3C2410_REGBASE, 0x0b000008)/*********************************//* I/O Ports Control Registers *//*********************************/#define GPHCON REGL(S3C2410_REGBASE, 0x0E000070)#define GPHDAT REGL(S3C2410_REGBASE, 0x0E000074)#define GPHUP REGL(S3C2410_REGBASE, 0x0E000078)#define GPFCON REGW(S3C2410_REGBASE, 0x0E000050)#define GPFDAT REGL(S3C2410_REGBASE, 0x0E000054)#define GPFUP REGL(S3C2410_REGBASE, 0x0E000058)#define GPGCON REGL(S3C2410_REGBASE, 0X0E000060)#define GPGUP REGL(S3C2410_REGBASE, 0X0E000068)#define EXTINT1 REGL(S3C2410_REGBASE, 0X0E00008c)#define EINTMASK REGL(S3C2410_REGBASE, 0X0E0000a4)#define EINTPEND REGL(S3C2410_REGBASE, 0X0E0000a8)/*********************************//* PWM Timer Control Registers *//*********************************/#define TCFG0 REGL(S3C2410_REGBASE, 0x09000000)#define TCFG1 REGL(S3C2410_REGBASE, 0x09000004)#define TCON REGL(S3C2410_REGBASE, 0x09000008)#define TCNTB0 REGW(S3C2410_REGBASE, 0x0900000c)#define TCMPB0 REGW(S3C2410_REGBASE, 0x09000010)#define TCNTO0 REGW(S3C2410_REGBASE, 0x09000014)#define TCNTB1 REGW(S3C2410_REGBASE, 0x09000018)#define TCMPB1 REGW(S3C2410_REGBASE, 0x0900001c)#define TCNTO1 REGW(S3C2410_REGBASE, 0x09000020)#define TCNTB2 REGW(S3C2410_REGBASE, 0x09000024)#define TCMPB2 REGW(S3C2410_REGBASE, 0x09000028)#define TCNTO2 REGW(S3C2410_REGBASE, 0x0900002c)#define TCNTB3 REGW(S3C2410_REGBASE, 0x09000030)#define TCMPB3 REGW(S3C2410_REGBASE, 0x09000034)#define TCNTO3 REGW(S3C2410_REGBASE, 0x09000038)#define TCNTB4 REGW(S3C2410_REGBASE, 0x0900003c)#define TCNTO4 REGW(S3C2410_REGBASE, 0x09000040)/*********************************//* USB Device Registers *//*********************************/#define USB_REGBASE (S3C2410_REGBASE+0x0A000000)#ifdef __BIG_ENDIAN#define FUNC_ADDR_REG REGB(USB_REGBASE, 0x143)#define PWR_REG REGB(USB_REGBASE, 0x147)#define EP_INT_REG REGB(USB_REGBASE, 0x14B)#define USB_INT_REG REGB(USB_REGBASE, 0x15B)#define EP_INT_EN_REG REGB(USB_REGBASE, 0x15F)#define USB_INT_EN_REG REGB(USB_REGBASE, 0x16F)#define FRAME_NUM1_REG REGB(USB_REGBASE, 0x173)#define FRAME_NUM2_REG REGB(USB_REGBASE, 0x177)#define INDEX_REG REGB(USB_REGBASE, 0x17B)#define EP0_CSR REGB(USB_REGBASE, 0x187)#define IN_CSR1_REG REGB(USB_REGBASE, 0x187)#define IN_CSR2_REG REGB(USB_REGBASE, 0x18B)#define MAXP_REG REGB(USB_REGBASE, 0x18F)#define OUT_CSR1_REG REGB(USB_REGBASE, 0x193)#define OUT_CSR2_REG REGB(USB_REGBASE, 0x197)#define EP0_FIFO REGB(USB_REGBASE, 0x1C3)#define EP1_FIFO REGB(USB_REGBASE, 0x1C7)#define EP2_FIFO REGB(USB_REGBASE, 0x1CB)#define EP3_FIFO REGB(USB_REGBASE, 0x1CF)#define EP4_FIFO REGB(USB_REGBASE, 0x1D3)#define OUT_FIFO_CNT1_REG REGB(USB_REGBASE, 0x19B)#define OUT_FIFO_CNT2_REG REGB(USB_REGBASE, 0x19F)#define EP1_DMA_CON REGB(USB_REGBASE, 0x203)#define EP1_DMA_UNIT REGB(USB_REGBASE, 0x207)#define EP1_DMA_FIFO REGB(USB_REGBASE, 0x20B)#define EP1_DMA_TTC_L REGB(USB_REGBASE, 0x20F)#define EP1_DMA_TTC_M REGB(USB_REGBASE, 0x213)#define EP1_DMA_TTC_H REGB(USB_REGBASE, 0x217)#define EP2_DMA_CON REGB(USB_REGBASE, 0x21B)#define EP2_DMA_UNIT REGB(USB_REGBASE, 0x21F)#define EP2_DMA_FIFO REGB(USB_REGBASE, 0x223)#define EP2_DMA_TTC_L REGB(USB_REGBASE, 0x227)#define EP2_DMA_TTC_M REGB(USB_REGBASE, 0x22B)#define EP2_DMA_TTC_H REGB(USB_REGBASE, 0x22F)#define EP3_DMA_CON REGB(USB_REGBASE, 0x243)#define EP3_DMA_UNIT REGB(USB_REGBASE, 0x247)#define EP3_DMA_FIFO REGB(USB_REGBASE, 0x24B)#define EP3_DMA_TTC_L REGB(USB_REGBASE, 0x24F)#define EP3_DMA_TTC_M REGB(USB_REGBASE, 0x253)#define EP3_DMA_TTC_H REGB(USB_REGBASE, 0x257)#define EP4_DMA_CON REGB(USB_REGBASE, 0x25B)#define EP4_DMA_UNIT REGB(USB_REGBASE, 0x25F)#define EP4_DMA_FIFO REGB(USB_REGBASE, 0x263)#define EP4_DMA_TTC_L REGB(USB_REGBASE, 0x267)#define EP4_DMA_TTC_M REGB(USB_REGBASE, 0x26B)#define EP4_DMA_TTC_H REGB(USB_REGBASE, 0x26F)#else#define FUNC_ADDR_REG REGB(USB_REGBASE, 0x140)#define PWR_REG REGB(USB_REGBASE, 0x144)#define EP_INT_REG REGB(USB_REGBASE, 0x148)#define USB_INT_REG REGB(USB_REGBASE, 0x158)#define EP_INT_EN_REG REGB(USB_REGBASE, 0x15C)#define USB_INT_EN_REG REGB(USB_REGBASE, 0x16C)#define FRAME_NUM1_REG REGB(USB_REGBASE, 0x170)#define FRAME_NUM2_REG REGB(USB_REGBASE, 0x174)#define INDEX_REG REGB(USB_REGBASE, 0x178)#define EP0_CSR REGB(USB_REGBASE, 0x184)#define IN_CSR1_REG REGB(USB_REGBASE, 0x184)#define IN_CSR2_REG REGB(USB_REGBASE, 0x188)#define MAXP_REG REGB(USB_REGBASE, 0x18C)#define OUT_CSR1_REG REGB(USB_REGBASE, 0x190)#define OUT_CSR2_REG REGB(USB_REGBASE, 0x194)#define OUT_FIFO_CNT1_REG REGB(USB_REGBASE, 0x198)#define OUT_FIFO_CNT2_REG REGB(USB_REGBASE, 0x19C)#define EP0_FIFO REGB(USB_REGBASE, 0x1C0)#define EP1_FIFO REGB(USB_REGBASE, 0x1C4)#define EP2_FIFO REGB(USB_REGBASE, 0x1C8)#define EP3_FIFO REGB(USB_REGBASE, 0x1CC)#define EP4_FIFO REGB(USB_REGBASE, 0x1D0)#define EP1_DMA_CON REGB(USB_REGBASE, 0x200)#define EP1_DMA_UNIT REGB(USB_REGBASE, 0x204)#define EP1_DMA_FIFO REGB(USB_REGBASE, 0x208)#define EP1_DMA_TTC_L REGB(USB_REGBASE, 0x20C)#define EP1_DMA_TTC_M REGB(USB_REGBASE, 0x210)#define EP1_DMA_TTC_H REGB(USB_REGBASE, 0x214)#define EP2_DMA_CON REGB(USB_REGBASE, 0x218)#define EP2_DMA_UNIT REGB(USB_REGBASE, 0x21C)#define EP2_DMA_FIFO REGB(USB_REGBASE, 0x220)#define EP2_DMA_TTC_L REGB(USB_REGBASE, 0x224)#define EP2_DMA_TTC_M REGB(USB_REGBASE, 0x228)#define EP2_DMA_TTC_H REGB(USB_REGBASE, 0x22C)#define EP3_DMA_CON REGB(USB_REGBASE, 0x240)#define EP3_DMA_UNIT REGB(USB_REGBASE, 0x244)#define EP3_DMA_FIFO REGB(USB_REGBASE, 0x248)#define EP3_DMA_TTC_L REGB(USB_REGBASE, 0x24C)#define EP3_DMA_TTC_M REGB(USB_REGBASE, 0x250)#define EP3_DMA_TTC_H REGB(USB_REGBASE, 0x254)#define EP4_DMA_CON REGB(USB_REGBASE, 0x258)#define EP4_DMA_UNIT REGB(USB_REGBASE, 0x25C)#define EP4_DMA_FIFO REGB(USB_REGBASE, 0x260)#define EP4_DMA_TTC_L REGB(USB_REGBASE, 0x264)#define EP4_DMA_TTC_M REGB(USB_REGBASE, 0x268)#define EP4_DMA_TTC_H REGB(USB_REGBASE, 0x26C)#endif/*********************************//* DMA Device Registers *//*********************************/#define DMA_REGBASE (S3C2410_REGBASE+0x03000000)#define DISRC0 REGL(DMA_REGBASE, 0x00)#define DISRCC0 REGL(DMA_REGBASE, 0x04)#define DIDST0 REGL(DMA_REGBASE, 0x08)#define DIDSTC0 REGL(DMA_REGBASE, 0x0C)#define DCON0 REGL(DMA_REGBASE, 0x10)#define DSTAT0 REGL(DMA_REGBASE, 0x14)#define DCSRC0 REGL(DMA_REGBASE, 0x18)#define DCDST0 REGL(DMA_REGBASE, 0x1C)#define DMASKTRIG0 REGL(DMA_REGBASE, 0x20)#define DISRC1 REGL(DMA_REGBASE, 0x40)#define DISRCC1 REGL(DMA_REGBASE, 0x44)#define DIDST1 REGL(DMA_REGBASE, 0x48)#define DIDSTC1 REGL(DMA_REGBASE, 0x4C)#define DCON1 REGL(DMA_REGBASE, 0x50)#define DSTAT1 REGL(DMA_REGBASE, 0x54)#define DCSRC1 REGL(DMA_REGBASE, 0x58)#define DCDST1 REGL(DMA_REGBASE, 0x5C)#define DMASKTRIG1 REGL(DMA_REGBASE, 0x60)#define DISRC2 REGL(DMA_REGBASE, 0x80)#define DISRCC2 REGL(DMA_REGBASE, 0x84)#define DIDST2 REGL(DMA_REGBASE, 0x88)#define DIDSTC2 REGL(DMA_REGBASE, 0x8C)#define DCON2 REGL(DMA_REGBASE, 0x90)#define DSTAT2 REGL(DMA_REGBASE, 0x94)#define DCSRC2 REGL(DMA_REGBASE, 0x98)#define DCDST2 REGL(DMA_REGBASE, 0x9C)#define DMASKTRIG2 REGL(DMA_REGBASE, 0xA0)#define DISRC3 REGL(DMA_REGBASE, 0xC0)#define DISRCC3 REGL(DMA_REGBASE, 0xC4)#define DIDST3 REGL(DMA_REGBASE, 0xC8)#define DIDSTC3 REGL(DMA_REGBASE, 0xCC)#define DCON3 REGL(DMA_REGBASE, 0xD0)#define DSTAT3 REGL(DMA_REGBASE, 0xD4)#define DCSRC3 REGL(DMA_REGBASE, 0xD8)#define DCDST3 REGL(DMA_REGBASE, 0xDC)#define DMASKTRIG3 REGL(DMA_REGBASE, 0xE0)#define SIZE_BOOT_SRAM 0x1000#define INT_ENABLE(irq) (INTMSK &= ~(1 << (irq)))#define INT_DISABLE(irq) (INTMSK |= 1 << (irq))#define CLEAR_PENDING(irq) (SRCPND = 1 << (irq), INTPND = 1 << (irq))#endif /* S3C2410_H */⌨️ 快捷键说明
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