head.s.svn-base

usb drivers based on s3c2410

#include "config.h"

#define hanlder(offset)		\
    sub sp, sp, #4;			\
    stmfd sp!, {r0};		\
    adr r0, evt;			\
	add r0, r0, #(offset);	\
    ldr r0, [r0];			\
    str r0, [sp, #4];		\
    ldmfd sp!, {r0, pc}

.global _start
.global evt

_start:
	b	reset
	b	undef
  	b	swi
	b	pabt
	b	dabt
	b	.
	b	irq
	b	fiq

evt:
	.long 0x00 @ NOT used
	.long 0x04
	.long 0x08
	.long 0x0c
	.long 0x10
	.long 0x14 @ NOT used
	.long 0x18
	.long 0x1c

undef:
	hanlder(0x4)
swi:
	hanlder(0x8)
pabt:
	hanlder(0xc)
dabt:
	hanlder(0x10)
irq:
	hanlder(0x18)
fiq:
	hanlder(0x1c)

reset:
	@ disable watch dog timer
	ldr	r0, =WTCON
	ldr	r1, =0x0
	str	r1, [r0]

	@ adjust locktime
	ldr	r0, =LOCKTIME
	ldr	r1, =0x00ffffff
	str	r1, [r0]
	
	@ PCLK:HCLK:FCLK = 1:2:4
	ldr	r0, =CLKDIVN
	ldr	r1, =0x3
	str	r1, [r0]
	
	@ asynchronous bus mode
	mrc	p15, 0, r0, c1, c0, 0		@ read ctrl register
	orr	r0, r0, #0xc0000000		@ Asynchronous
	mcr	p15, 0, r0, c1, c0, 0		@ write ctrl register	
	
	@ CPU clock to 200Mhz
	ldr	r0, =MPLLCON
	ldr	r1, =((P_MDIV<<12)|(P_PDIV<<4)|P_SDIV)
	str	r1, [r0]

	@ initialise memory
	bl	memsetup

	ldr sp, =SIZE_BOOT_SRAM

	bl main

die:
	b die

memsetup:
	ldr	r1, =BWSCON
	adrl	r2, mem_cfg_val
	add	r3, r1, #52
1:
	ldr	r4, [r2], #4
	str	r4, [r1], #4
	cmp	r1, r3
	bne	1b

	mov	pc, lr

@
@ Memory configuration values
@
.align 4
mem_cfg_val:
	.long	((B7_ST<<31)+(B7_WS<<30)+(B7_DW<<28)+(B6_ST<<27)+(B6_WS<<26)+(B6_DW<<24)+(B5_ST<<23)+(B5_WS<<22)+(B5_DW<<20)+(B4_ST<<19)+(B4_WS<<18)+(B4_DW<<16)+(B3_ST<<15)+(B3_WS<<14)+(B3_DW<<12)+(B2_ST<<11)+(B2_WS<<10)+(B2_DW<<8)+(B1_ST<<7)+(B1_WS<<6)+(B1_DW<<4)+(B0_DW<<1)+(0))  @BWSCON
	.long	((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tcah<<4)+(B0_Tacp<<2)+(B0_PMC))  @GCS0
	.long	((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tcah<<4)+(B1_Tacp<<2)+(B1_PMC))  @GCS1
	.long	((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tcah<<4)+(B2_Tacp<<2)+(B2_PMC))  @GCS2
	.long	((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tcah<<4)+(B3_Tacp<<2)+(B3_PMC))  @GCS3
	.long	((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tcah<<4)+(B4_Tacp<<2)+(B4_PMC))  @GCS4
	.long	((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tcah<<4)+(B5_Tacp<<2)+(B5_PMC))  @GCS5
#if B6_MT==MT_SDRAM
	.long	((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))                                                        @GCS6
#endif /*B6_MT*/
#if B7_MT==MT_SDRAM
	.long	((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))                                                        @GCS7
#endif /*B7_MT*/
	.long	((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Tsrc<<18)+REFCNT)                                      @REFRESH
	.long	((BURST_EN<<7)+(SCKE_EN<<5)+(SCLK_EN<<4)+(BK76MAP))                                         @BANKSIZE                            @BANKSIZE
	.long	((B6_WBL<<9)+(B6_TM<<7)+(B6_CL<<4)+(B6_BT<<3)+(B6_BL))                                      @MRSRB6
	.long	((B7_WBL<<9)+(B7_TM<<7)+(B7_CL<<4)+(B7_BT<<3)+(B7_BL))                                      @MRSRB7