ml69q6203.h

最新版IAR FOR ARM（EWARM）5.11中的代码例子

/*****************************************************/
/*    SSIO control register                          */
/*****************************************************/
#define SSIO_BASE   (0xB7B10000)        /* base address */
#define SSIOBUF0    (SSIO_BASE+0x00)    /* transmiting/receiving buffer register (RW,8,0x00) */
#define SSIOSTA0    (SSIO_BASE+0x04)    /* SSIO status register (RW,8,0x00) */
#define SSIOCON0    (SSIO_BASE+0x08)    /* SSIO control register (RW,8,0x00) */
#define SSIOINT0    (SSIO_BASE+0x0C)    /* SSIO interrupt demand register (RW,8,0x00) */
#define SSIOINTEN0  (SSIO_BASE+0x10)    /* SSIO interrupt enable register (RW,8,0x00) */
#define SSIODMAC0   (SSIO_BASE+0x14)    /* SSIO DMA transmit register (RW,8,0x00) */
#define SSIOTSCON0  (SSIO_BASE+0x18)    /* SSIO test control register (RW,8,0x00) */
#define SSIOBUF1    (SSIO_BASE+0x20)    /* transmiting/receiving buffer register (RW,8,0x00) */
#define SSIOSTA1    (SSIO_BASE+0x24)    /* SSIO status register (RW,8,0x00) */
#define SSIOCON1    (SSIO_BASE+0x28)    /* SSIO control register (RW,8,0x00) */
#define SSIOINT1    (SSIO_BASE+0x2C)    /* SSIO interrupt demand register (RW,8,0x00) */
#define SSIOINTEN1  (SSIO_BASE+0x30)    /* SSIO interrupt enable register (RW,8,0x00) */
#define SSIODMAC1   (SSIO_BASE+0x34)    /* SSIO DMA transmit register (RW,8,0x00) */
#define SSIOTSCON1  (SSIO_BASE+0x38)    /* SSIO test control register (RW,8,0x00) */

/* bit field of SSIOBUF0,SSIOBUF1 register */
#define SSIOSTA_DUMMY   (0xFF)

/* bit field of SSIOSTA0,SSIOSTA1 register */
#define SSIOSTA_BUSY    (0x01)          /* transmiting/receiving buffer busy */
#define SSIOSTA_SFCT0   (0x00)          /* transmit end or not transmitted */
#define SSIOSTA_SFCT1   (0x20)          /* 1bit transmit end */
#define SSIOSTA_SFCT2   (0x40)          /* 2bit transmit end */
#define SSIOSTA_SFCT3   (0x60)          /* 3bit transmit end */
#define SSIOSTA_SFCT4   (0x80)          /* 4bit transmit end */
#define SSIOSTA_SFCT5   (0xA0)          /* 5bit transmit end */
#define SSIOSTA_SFCT6   (0xC0)          /* 6bit transmit end */
#define SSIOSTA_SFCT7   (0xE0)          /* 7bit transmit end */

/* bit field of SSIOCON0,SSIOCON1 register */
#define SSIOCON_TCK0    (0x00)          /* selected  15    MHz for sync clock */
#define SSIOCON_TCK1    (0x01)          /* selected   7.5  MHz for sync clock */
#define SSIOCON_TCK2    (0x02)          /* selected   3.75 MHz for sync clock */
#define SSIOCON_TCK3    (0x03)          /* selected 937.5  kHz for sync clock */
#define SSIOCON_TCK4    (0x04)          /* selected 468.75 kHz for sync clock */
#define SSIOCON_TCK5    (0x05)          /* selected 117.18 kHz for sync clock */
#define SSIOCON_TCK7    (0x07)          /* selected TMOUTx for sync clock */
#define SSIOCON_MASTER  (0x00)          /* Master */
#define SSIOCON_SLAVE   (0x10)          /* Slave */
#define SSIOCON_LSBFST  (0x00)          /* LSB first */
#define SSIOCON_MSBFST  (0x20)          /* MSB first */
#define SSIOCON_SCKNML  (0x00)          /* normal clock */
#define SSIOCON_SCKINV  (0x40)          /* clock inverted */
#define SSIOCON_RSTOFF  (0x00)          /* serial reset off */
#define SSIOCON_RSTON   (0x80)          /* serial reset on  */


/* bit field of SSIOINT0,SSIOINT1 register */
#define SSIOINT_TXRXCMP (0x01)          /* transmit/receive complete */
#define SSIOINT_TREMP   (0x02)          /* transmit empty */

/* bit field of SSIOINTEN0,SSIOINTEN1 register */
#define SSIOINTEN_TXRXCMPEN (0x01)      /* transmit/receive complete enable */
#define SSIOINTEN_TREMPEN   (0x02)      /* transmit empty enable */

/* bit field of SSIODMAC0, SSIODMAC1 register */
#define SSIODMAC_DMAEN   (0x00)         /* DMA transfer mode desable */
#define SSIODMAC_DMADES  (0x01)         /* DMA transfer mode enable */
#define SSIODMAC_TRNSACT (0x00)         /* DMA transmit action */
#define SSIODMAC_RCVACT  (0x10)         /* DMA receive action */

/* bit field of SSIOTSCON0,SSIOTSCON01 register */
#define SSIOTSCON_LBTST (0x80)          /* loop back test mode on*/
#define SSIOTSCON_NOTST (0x00)          /* test mode off */

/*****************************************************/
/*    I2C control register                          */
/*****************************************************/
#define I2C_BASE    (0xB7B00000)        /* base address */
#define I2CCON      (I2C_BASE+0x00)     /* I2C control register (RW,8,0x00) */
#define I2CSAD      (I2C_BASE+0x04)     /* I2C slave address mode setting register (RW,8,0x00) */
#define I2CCLR      (I2C_BASE+0x08)     /* I2C transmit speed setting register (RW,8,0x00) */
#define I2CSR       (I2C_BASE+0x0C)     /* I2C status register (R,8,0x00) */
#define I2CIR       (I2C_BASE+0x10)     /* I2C interrupt demand register (RW,8,0x00) */
#define I2CIMR      (I2C_BASE+0x14)     /* I2C interrupt mask register  (RW,8,0x00) */
#define I2CDR       (I2C_BASE+0x18)     /* I2C transmiting/receiving buffer register (RW,8,0x00) */

/* bit field of I2CCON register */
#define I2CCON_EN       (0x01)          /* restart sequence start */
#define I2CCON_OC       (0x02)          /* I2C-bus hold */
#define I2CCON_STCM     (0x04)          /* communication start */
#define I2CCON_RESTR    (0x08)          /* carry out restart */
#define I2CCON_START    (0x10)          /* exist START byte */

/* bit field of I2CSAD register */
#define I2CSAD_RW_SND   (0x00)          /* data transmiting mode */
#define I2CSAD_RW_REC   (0x01)          /* data receiving mode */
#define I2CSAD_SLVAD0   (0x02)          /* slave address 0 */
#define I2CSAD_SLVAD1   (0x04)          /* slave address 1 */
#define I2CSAD_SLVAD2   (0x08)          /* slave address 2 */
#define I2CSAD_SLVAD3   (0x10)          /* slave address 3 */
#define I2CSAD_SLVAD4   (0x20)          /* slave address 4 */
#define I2CSAD_SLVAD5   (0x40)          /* slave address 5 */
#define I2CSAD_SLVAD6   (0x80)          /* slave address 6 */

/* bit field of I2CCLR register */
#define I2CCLR_CMD1 (0x00)              /* Standard-mode */
#define I2CCLR_CMD4 (0x01)              /* Fast-mode */

/* bit field of I2CSR register */
#define I2CSR_DAK   (0x01)              /* data ACKnowledge no receive */
#define I2CSR_AAK   (0x02)              /* slave address ACKnowledge no receive */

/* bit field of I2CIR register */
#define I2CIR_IR    (0x01)              /* interrupt demand */

/* bit field of I2CIMR register */
#define I2CIMR_MF   (0x01)              /* interrupt mask set */


/*****************************************************/
/*    RTC Control register                           */
/*****************************************************/
#define RTC_BASE    (0xB7C00000)        /* base address */
#define RTCREG      (RTC_BASE+0x00)     /* RTC second count register  */
#define RTCCON      (RTC_BASE+0x04)     /* RTC control register  */
#define RTCCMP      (RTC_BASE+0x08)     /* RTC compare register  */
#define RTCSCRP     (RTC_BASE+0x0C)     /* RTC scratchpad register  */
#define RTCST       (RTC_BASE+0x10)     /* RTC status register  */

/* for RTCREG, RTCCON, RTCCMP, RTCST registers */
#define RTC_UNLOCK1     0x0000003c
#define RTC_UNLOCK2     0x0000005a

/*****************************************************/
/*    I2S send control register                      */
/*****************************************************/
#define I2SSND_BASE (0x82000000)     /* base address */
#define I2SFIFOO    (I2SSND_BASE+0x00)  /* I2S transceiver FIFO register (RW,32,---) */
#define I2SCONO0    (I2SSND_BASE+0x04)  /* I2S transceiver contorl register0 (RW,32,0x0000) */
#define I2SCONO1    (I2SSND_BASE+0x08)  /* I2S transceiver control register1 (RW,32,0x0000) */
#define I2SAFRO     (I2SSND_BASE+0x0C)  /* I2S transceiver Almost Full threshold register (RW,32,0x0000) */
#define I2SAERO     (I2SSND_BASE+0x10)  /* I2S transceiver Almost Empty threshold register (RW,32,0x0000) */
#define I2SIMRO     (I2SSND_BASE+0x14)  /* I2S transceiver interrupt mask register (RW,32,0x000F) */
#define I2SISTO     (I2SSND_BASE+0x18)  /* I2S transceiver interrupt status register (RW,32,0x0000) */
#define I2SWADRO    (I2SSND_BASE+0x1C)  /* I2S transceiver FIFO write address register (RW,32,0x0000) */
#define I2SRADRO    (I2SSND_BASE+0x20)  /* I2S transceiver FIFO read address register (RW,32,0x0000) */
#define I2SDNOO     (I2SSND_BASE+0x24)  /* I2S transceiver FIFO occupation data size register (R,32,0x0000) */

/*****************************************************/
/*    I2S receive control register                   */
/*****************************************************/
#define I2SRCV_BASE (0x84000000)        /* base address */
#define I2SFIFOI    (I2SRCV_BASE+0x00)  /* I2S receiver FIFO register (RW,32,0x0000) */
#define I2SCONI0    (I2SRCV_BASE+0x04)  /* I2S receiver contorl register0 (RW,32,0x0000) */
#define I2SCONI1    (I2SRCV_BASE+0x08)  /* I2S receiver control register1 (RW,32,0x0000) */
#define I2SAFRI     (I2SRCV_BASE+0x0C)  /* I2S receiver Almost Full threshold register (RW,32,0x0000) */
#define I2SAERI     (I2SRCV_BASE+0x10)  /* I2S receiver Almost Empty threshold register (RW,32,0x0000) */
#define I2SIMRI     (I2SRCV_BASE+0x14)  /* I2S receiver interrupt mask register (RW,32,0x000F) */
#define I2SISTI     (I2SRCV_BASE+0x18)  /* I2S receiver interrupt status register (RW,32,0x0000) */
#define I2SWADRI    (I2SRCV_BASE+0x1C)  /* I2S receiver FIFO write address register (RW,32,0x0000) */
#define I2SRADRI    (I2SRCV_BASE+0x20)  /* I2S receiver FIFO read address register (RW,32,0x0000) */
#define I2SDNOI     (I2SRCV_BASE+0x24)  /* I2S receiver FIFO occupation data size register (R,32,0x0000) */


/*****************************************************/
/*    NAND FLASH Controller register                 */
/*****************************************************/
#define NFC_BASE    (0x86000000)        /* base address */
#define MBANK       (NFC_BASE+0x00)     /* media bank register (RW,32,0x0000) */
#define MSCTRL      (NFC_BASE+0x04)     /* media sequencer controller register (RW,32,0x0000) */
#define MSWAIT      (NFC_BASE+0x08)     /* media sequencer wait register (RW,32,0x0000) */
#define MSSTS       (NFC_BASE+0x0C)     /* media sequencer status register (R,32,0x001E) */
#define MINTENBL    (NFC_BASE+0x10)     /* media sequencer interrupt enable register (RW,32,0x0000) */
#define MSERR       (NFC_BASE+0x14)     /* media sequencer error status register (R,32,0x0000) */
#define MMCMD       (NFC_BASE+0x18)     /* media command register (W,32,---) */
#define MMADR       (NFC_BASE+0x1C)     /* media address register (W,32,---) */
#define MMSEL       (NFC_BASE+0x20)     /* media select register (RW,32,0x0000) */
#define MMRDCTL     (NFC_BASE+0x24)     /* media data read control register (RW,32,0x0000) */
#define MOPTION     (NFC_BASE+0x28)     /* media option register (RW,32,0x0000) */
#define MMRDDATA    (NFC_BASE+0x2C)     /* media read data store register (R,32,0x0000 */
#define ECCLP1      (NFC_BASE+0x30)     /* ECC line parity register1 (R,32,0xFFFFFFFF) */
#define ECCCP1      (NFC_BASE+0x34)     /* ECC column parity register1 (R,32,0x003F003F)) */
#define ECCERR1     (NFC_BASE+0x38)     /* ECC error pointer register1 (R,32,0x0000) */
#define HREV1       (NFC_BASE+0x40)     /* redundancy reserve data register1 (RW,32,0x0000) */
#define HSTAD1      (NFC_BASE+0x44)     /* redundancy data /block-status.address register1 (RW,32,0x0000) */
#define HECC2       (NFC_BASE+0x48)     /* redundancy ECC2-High, ECC2-Low block address register (RW,32,0x0000) */
#define HECC1       (NFC_BASE+0x4C)     /* redundancy ECC1-High, ECC1-Low block address register (RW,32,0x0000) */
#define ECCLP3      (NFC_BASE+0x50)     /* ECC line parity register3 (R,32,0xFFFFFFFF) */
#define ECCCP3      (NFC_BASE+0x54)     /* ECC column parity register3 (R,32,0x003F003F)) */
#define ECCERR3     (NFC_BASE+0x58)     /* ECC error pointer register3 (R,32,0x0000) */
#define HREV3       (NFC_BASE+0x60)     /* redundancy reserve data register3 (RW,32,0x0000) */
#define HSTAD3      (NFC_BASE+0x64)     /* redundancy data/block status block address register (RW,32,0x0000) */

/*****************************************************/
/*    interrupt number                               */
/*****************************************************/
#define INT_SYSTEM_TIMER    0
#define INT_SSIO_0          1
#define INT_SSIO_1          2
#define INT_SSIO_2          3
#define INT_WDT             4
#define INT_RTC             5
#define INT_PIOE12          6
    /* reserved             7   */
#define INT_IRQS            8
#define INT_PWM             9
#define INT_SIO             10
#define INT_I2C             11
#define INT_ADC             12
#define INT_NANDFLASH       13
#define INT_IDEC            14
    /* reserved             15  */
#define INT_TIMER0          16
#define INT_TIMER1          17
#define INT_TIMER2          18
    /* reserved             19  */
#define INT_I2STRANS        20
#define INT_I2SRECEIVE      21
#define INT_DMA0            22
#define INT_DMA1            23
#define INT_DMA2            24
#define INT_DMA3            25
#define INT_PIOE15          26
#define INT_USBVBUS         26  /* same as PIOE15, we sense VBUS by PIOE15 */
#define INT_USB             27
    /* reserved             28  */
#define INT_PIOE14          29
    /* reserved             30  */
#define INT_PIOE13          31

/*****************************************************/
/*    other                                          */
/*****************************************************/
//#define UNLOCK      (0x3C)              /* unlock protect for mis-write */

#ifdef __cplusplus
};      /* End of 'extern "C"' */
#endif
#endif  /* End of ML69Q6203_H */