📄 ml69q6203.h
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/* bit field of GPPIA/GPPIB/GPPIC/GPPID/GPPIE register */
#define GPPIA_GPPIA (0xFFFF) /* GPPIA[15:0] */
#define GPPIB_GPPIB (0xFFFF) /* GPPIB[15:0] */
#define GPPIC_GPPIC (0xFFFF) /* GPPIC[15:0] */
#define GPPID_GPPID (0xFFFF) /* GPPID[15:0] */
#define GPPIE_GPPIE (0xFFFF) /* GPPIE[15:0] */
#define GPPIF_GPPIF (0x007F) /* GPPIF[ 6:0] */
/* bit field of GPPMA/GPPMB/GPPMC/GPPMD/GPPME/GPPMF register */
#define GPPMA_GPPMA (0xFFFF) /* GPPMA[15:0] 0:input, 1:output */
#define GPPMB_GPPMB (0xFFFF) /* GPPMB[15:0] 0:input, 1:output */
#define GPPMC_GPPMC (0xFFFF) /* GPPMC[15:0] 0:input, 1:output */
#define GPPMD_GPPMD (0xFFFF) /* GPPMD[15:0] 0:input, 1:output */
#define GPPME_GPPME (0xFFFF) /* GPPME[15:0] 0:input, 1:output */
#define GPPMF_GPPMF (0x00FF) /* GPPME[ 7:0] 0:input, 1:output */
/* bit field of GPIEE register */
#define GPIEE_GPIEE (0x0F00) /* GPIEE[15:12] 0:interrupt disable, 1:interrupt enable */
/* bit field of GPIPE register */
#define GPIPE_GPIPE (0x0F00) /* GPIPE[15:12] 0:"L"level, 1: "H"level */
/* bit field of GPISE register */
#define GPISE_GPISE (0x0F00) /* GPISE[15:12] 0:interrupt not occurred, 1:interrupt occurred */
/* bit field of GPIME register */
#define GPIME_GPIME (0x0F00) /* GPISE[15:12] 0:edge detect mode, 1:level detect mode */
/*****************************************************/
/* Watch Dog Timer control register */
/*****************************************************/
#define WDT_BASE (0xB7E00000) /* base address */
#define WDTCON (WDT_BASE+0x00) /* Watch Dog Timer control register (W,8,--) */
#define WDTBCON (WDT_BASE+0x04) /* time base counter control register (RW,8,0x00) */
#define WDSTAT (WDT_BASE+0x14) /* Watch Dog Timer status register (RW,8,0x00) */
/* bit field of WDTCON */
#define WDTCON_0xC3 (0xC3) /* 0xC3 */
#define WDTCON_0x3C (0x3C) /* 0x3C */
/* bit field of WDTBCON */
#define WDTBCON_UNLOCK (0x5A) /* enable writing to this register */
#define WDTBCON_CLK75 (0x00) /* CCLK/(=7.5MHz) */
#define WDTBCON_CLK4 (0x01) /* CCLK/4 */
#define WDTBCON_CLK32 (0x02) /* CCLK/32 */
#define WDTBCON_CLK64 (0x03) /* CCLK/64 */
#define WDTBCON_WDTM (0x00) /* WDT mode */
#define WDTBCON_ITM (0x08) /* interval timer mode */
#define WDTBCON_ITDIS (0x00) /* disable interval timer */
#define WDTBCON_ITEN (0x10) /* enable interval timer */
#define WDTBCON_INT (0x00) /* generate interrupt */
#define WDTBCON_RESET (0x40) /* system reset */
#define WDTBCON_COUNT (0x00) /* timer count */
#define WDTBCON_WDHLT (0x80) /* timer stop */
/* bit field of WDTSTAT */
#define WDSTAT_RSTWDT (0x01) /* reset by WDT */
#define WDSTAT_RSTPWON (0x00) /* reset by power on */
#define WDSTAT_WDTIST (0x10) /* WDT interrupt */
#define WDSTAT_IVTIST (0x20) /* IVT interrupt */
/*****************************************************/
/* system timer control register */
/*****************************************************/
#define STCR_BASE (0xB8001000) /* base address */
#define TMEN (STCR_BASE+0x04) /* timer enable register (RW,16,0x0000) */
#define TMRLR (STCR_BASE+0x08) /* timer reload register (RW,16,0x0000) */
#define TMOVF (STCR_BASE+0x10) /* overflow register (RW,16,0x0000) */
/* bit field of TMEN register */
#define TMEN_TCEN (0x0001) /* timer enabled */
#define TMEN_TCDSBL (0x0000) /* timer disabled */
/* these are aliases */
#define TMEN_RUN (0x0001) /* timer enabled */
#define TMEN_STOP (0x0000) /* timer disabled */
/* bit field of TMOVF register */
#define TMOVF_OVF (0x0001) /* overflow generated */
#define TMOVF_NOOVF (0x0000) /* no overflow generated */
/*****************************************************/
/* timer control register */
/*****************************************************/
#define TCR_BASE (0xB7F00000) /* base address */
#define TIMECNTL0 (TCR_BASE+0x00) /* timer0 control register (RW,16,0x0000) */
#define TIMEBASE0 (TCR_BASE+0x04) /* timer0 base register (RW,16,0x0000) */
#define TIMECNT0 (TCR_BASE+0x08) /* timer0 counter register (R,16,0x0000) */
#define TIMECMP0 (TCR_BASE+0x0C) /* timer0 compare register (RW,16,0xFFFF) */
#define TIMESTAT0 (TCR_BASE+0x10) /* timer0 status register (RW,16,0x0000) */
#define TIMECNTL1 (TCR_BASE+0x20) /* timer1 control register (RW,16,0x0000) */
#define TIMEBASE1 (TCR_BASE+0x24) /* timer1 base register (RW,16,0x0000) */
#define TIMECNT1 (TCR_BASE+0x28) /* timer1 counter register (R,16,0x0000) */
#define TIMECMP1 (TCR_BASE+0x2C) /* timer1 compare register (RW,16,0xFFFF) */
#define TIMESTAT1 (TCR_BASE+0x30) /* timer1 status register (RW,16,0x0000) */
#define TIMECNTL2 (TCR_BASE+0x40) /* timer2 control register (RW,16,0x0000) */
#define TIMEBASE2 (TCR_BASE+0x44) /* timer2 base register (RW,16,0x0000) */
#define TIMECNT2 (TCR_BASE+0x48) /* timer2 counter register (R,16,0x0000) */
#define TIMECMP2 (TCR_BASE+0x4C) /* timer2 compare register (RW,16,0xFFFF) */
#define TIMESTAT2 (TCR_BASE+0x50) /* timer2 status register (RW,16,0x0000) */
/* bit field of TIMECNTL0-2 register */
#define TIMECNTL_OS (0x0001) /* one shot timer */
#define TIMECNTL_INT (0x0000) /* interval timer */
#define TIMECNTL_START (0x0008) /* timer start */
#define TIMECNTL_STOP (0x0000) /* timer stop */
#define TIMECNTL_IE (0x0010) /* enable interrupt */
#define TIMECNTL_ID (0x0000) /* denable interrupt */
#define TIMECNTL_CLK (0x0000) /* CCLK(=7.5MHz or 2.048kHz) */
#define TIMECNTL_CLK2 (0x0020) /* CPUCLK/2 */
#define TIMECNTL_CLK4 (0x0040) /* CPUCLK/4 */
#define TIMECNTL_CLK8 (0x0060) /* CPUCLK/8 */
#define TIMECNTL_CLK16 (0x0080) /* CPUCLK/16 */
#define TIMECNTL_CLK64 (0x00A0) /* CPUCLK/64 */
#define TIMECNTL_CLK128 (0x00C0) /* CPUCLK/128 */
#define TIMECNTL_CLK256 (0x00E0) /* CPUCLK/256 */
/* bit field of TIMESTAT0-5 register */
#define TIMESTAT_STATUS (0x0001) /* status bit */
/*****************************************************/
/* PWM control register */
/*****************************************************/
#define PWM_BASE (0xB7D00000) /* base address */
#define PWR (PWM_BASE+0x00) /* PWM register (RW,16,0x0000) */
#define PWCY (PWM_BASE+0x04) /* PWM cycle register (RW,16,0x0000) */
#define PWC (PWM_BASE+0x08) /* PWM counter (RW,16,0x0000) */
#define PWCON (PWM_BASE+0x0C) /* PWM contrlo register (RW,16,0x0000) */
#define PWINTSTS (PWM_BASE+0x3C) /* PWM interrupt status register (RW,16,0x0000) */
/* bit field of PWCON register */
#define PWCON_PWR (0x0001) /* enable PWC */
/* this is alias */
#define PWCON_RUN (0x0001) /* enable PWC */
#define PWCON_CLK1 (0x0000) /* 1/1 CPUCLK */
#define PWCON_CLK4 (0x0002) /* 1/4 CPUCLK */
#define PWCON_CLK16 (0x0004) /* 1/16 CPUCLK */
#define PWCON_CLK32 (0x0006) /* 1/32 CPUCLK */
#define PWCON_INTIE (0x0040) /* enable interrupt */
#define PWCON_PWCOV (0x0080) /* interruput when PWC overflow */
/* bit field of PWINTSTS register */
#define PWINTSTS_INTS (0x0100) /* interrupt generated */
#define PWINTSTS_INTCLR (0x0001) /* interrupt clear */
/*****************************************************/
/* ASIO control register */
/*****************************************************/
#define SC_BASE (0xB8002000) /* base address */
#define SIOBUF (SC_BASE+0x00) /* transmiting/receiving buffer register (RW,16,0x0000) */
#define SIOSTA (SC_BASE+0x04) /* SIO status register (RW,16,0x0000) */
#define SIOCON (SC_BASE+0x08) /* SIO control register (RW,16,0x0000) */
#define SIOBCN (SC_BASE+0x0C) /* baud rate control register (RW,16,0x0000) */
#define SIOBT (SC_BASE+0x14) /* baud rate timer register (RW,16,0x0000) */
#define SIOTCN (SC_BASE+0x18) /* SIO test control register (RW,16,0x0000) */
/* bit field of SIOBUF register */
#define SIOBUF_SIOBUF (0x00FF) /* SIOBUF[7:0] */
/* bit field of SIOSTA register */
#define SIOSTA_FERR (0x0001) /* framing error */
#define SIOSTA_OERR (0x0002) /* overrun error */
#define SIOSTA_PERR (0x0004) /* parity error */
#define SIOSTA_RVIRQ (0x0010) /* receive ready */
#define SIOSTA_TRIRQ (0x0020) /* transmit ready */
/* bit field of SIOCON register */
#define SIOCON_LN7 (0x0001) /* data length : 7bit */
#define SIOCON_LN8 (0x0000) /* data length : 8bit */
#define SIOCON_PEN (0x0002) /* parity enabled */
#define SIOCON_PDIS (0x0000) /* parity disabled */
#define SIOCON_EVN (0x0004) /* even parity */
#define SIOCON_ODD (0x0000) /* odd parity */
#define SIOCON_TSTB1 (0x0008) /* stop bit : 1 */
#define SIOCON_TSTB2 (0x0000) /* stop bit : 2 */
/* bit field of SIOBCN register */
#define SIOBCN_BGRUN (0x0010) /* count start */
#define SIOBCN_BGSTOP (0x0000) /* count stop */
/* bit field of SIOBT register */
#define SIOBT_SIOBT (0x00FF) /* SIOBT[7:0] */
/* bit field of SIOTCN register */
#define SIOTCN_MFERR (0x0001) /* generate framin error */
#define SIOTCN_MPERR (0x0002) /* generate parity error */
#define SIOTCN_LBTST (0x0080) /* loop back test */
/*****************************************************/
/* ADC control register */
/*****************************************************/
#define ADC_BASE (0xB6000000) /* base address */
#define ADCON1 (ADC_BASE+0x04) /* ADC control 1 register (RW,16,0x0000) */
#define ADCON2 (ADC_BASE+0x08) /* ADC control 2 register (RW,16,0x0003) */
#define ADINT (ADC_BASE+0x0C) /* AD interrupt control register (RW,16,0x0000) */
#define ADR0 (ADC_BASE+0x14) /* AD Result 0 register (RW,16,0x0000) */
#define ADR1 (ADC_BASE+0x18) /* AD Result 1 register (RW,16,0x0000) */
#define ADR2 (ADC_BASE+0x1C) /* AD Result 2 register (RW,16,0x0000) */
#define ADR3 (ADC_BASE+0x20) /* AD Result 3 register (RW,16,0x0000) */
/* bit field of ADCON1 register */
#define ADCON1_ADSTM (0x0003) /* ADSTM[1:0] */
#define ADCON1_CH0 (0x0000) /* CH0 */
#define ADCON1_CH1 (0x0001) /* CH1 */
#define ADCON1_CH2 (0x0002) /* CH2 */
#define ADCON1_CH3 (0x0003) /* CH3 */
#define ADCON1_STS (0x0010) /* AD conversion start */
/* bit field of ADCON2 register */
#define ADCON2_ACKSEL (0x0003) /* ACKSEL[1:0] */
#define ADCON2_CLK2 (0x0001) /* CPUCLK/2 */
#define ADCON2_CLK4 (0x0002) /* CPUCLK/4 */
#define ADCON2_CLK8 (0x0003) /* CPUCLK/8 */
/* bit field of ADINT register */
//#define ADINT_INTSN (0x0001) /* AD conversion of ch7 finished (scan mode) */
#define ADINT_INTST (0x0002) /* AD conversion finished (select mode) */
//#define ADINT_ADSNIE (0x0004) /* enable interrupt (scan mode) */
#define ADINT_ADSTIE (0x0008) /* enable interrupt (select mode) */
/* bit field of ADR0,ADR1,ADR2,ADR3 register */
#define ADR0_DT0 (0x03FF) /* DT0[9:0] AD result */
#define ADR1_DT1 (0x03FF) /* DT1[9:0] AD result */
#define ADR2_DT2 (0x03FF) /* DT2[9:0] AD result */
#define ADR3_DT3 (0x03FF) /* DT3[9:0] AD result */
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