📄 ml69q6203.h
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#define IDM_IRQ28 (0x00003000) /* IRQ28 */
#define IDM_IRQ31 (0x0000C000) /* IRQ31 */
/* bit field of ILC register */
#define ILC_ILC16 (0x00000007) /* IRQ16, IRQ17 */
#define ILC_ILC18 (0x00000070) /* IRQ18, IRQ19 */
#define ILC_ILC20 (0x00000700) /* IRQ20, IRQ21 */
#define ILC_ILC22 (0x00007000) /* IRQ22, IRQ23 */
#define ILC_ILC24 (0x00070000) /* IRQ24, IRQ25 */
#define ILC_ILC26 (0x00700000) /* IRQ26, IRQ27 */
#define ILC_ILC28 (0x07000000) /* IRQ28, IRQ29 */
#define ILC_ILC30 (0x70000000) /* IRQ30, IRQ31 */
#define ILC_INT_LV1 (0x11111111) /* interrupt level 1 */
#define ILC_INT_LV2 (0x22222222) /* interrupt level 2 */
#define ILC_INT_LV3 (0x33333333) /* interrupt level 3 */
#define ILC_INT_LV4 (0x44444444) /* interrupt level 4 */
#define ILC_INT_LV5 (0x55555555) /* interrupt level 5 */
#define ILC_INT_LV6 (0x66666666) /* interrupt level 6 */
#define ILC_INT_LV7 (0x77777777) /* interrupt level 7 */
/*****************************************************/
/* external memory control register */
/*****************************************************/
#define EMCR_BASE (0x78100000) /* base address */
#define BWC (EMCR_BASE+0x00) /* bus width control register (RW,32,0x00000008) */
#define ROMAC (EMCR_BASE+0x04) /* external ROM access control register (RW,32,0x00000007) */
#define RAMAC (EMCR_BASE+0x08) /* external SRAM access control register (RW,32,0x00000007) */
#define IO0AC (EMCR_BASE+0x0C) /* external IO0 access control register (RW,32,0x00000007) */
#define IO1AC (EMCR_BASE+0x10) /* external IO1 access control register (RW,32,0x00000007) */
/* bit field of BWC register */
#define BWC_ROMBW0 (0x00000000) /* ROM disable */
#define BWC_ROMBW16 (0x00000008) /* ROM 16bit */
#define BWC_RAMBW0 (0x00000000) /* RAM disable */
#define BWC_RAMBW16 (0x00000020) /* RAM 16bit */
#define BWC_IO0BW0 (0x00000000) /* IO0 disable */
#define BWC_IO0BW8 (0x00000040) /* IO0 8bit */
#define BWC_IO0BW16 (0x00000080) /* IO0 16 bit */
#define BWC_IO1BW0 (0x00000000) /* IO1 disable */
#define BWC_IO1BW8 (0x00000100) /* IO1 8bit */
#define BWC_IO1BW16 (0x00000200) /* IO1 16bit */
/* bit field of ROMAC register */
#define ROMAC_ROMTYPE (0x00000007) /* ROMTYPE[2:0] */
/* bit field of RAMAC register */
#define RAMAC_RAMTYPE (0x00000007) /* RAMTYPE[2:0] */
/* bit field of IO0AC register */
#define IO0AC_IO0TYPE (0x00000007) /* IO0TYPE[2:0] */
/* bit field of IO1AC register */
#define IO1AC_IO1TYPE (0x00000007) /* IO1TYPE[2:0] */
/*****************************************************/
/* DRAM control register */
/*****************************************************/
#define DCR_BASE (0x78180000) /* base address */
#define DBWC (DCR_BASE+0x00) /* DRAM Bus Width control register (RW,32,0x00000000) */
#define DRMC (DCR_BASE+0x04) /* DRAM control register (RW,32,0x00000000) */
#define DRPC (DCR_BASE+0x08) /* DRAM Attribute parameter Setup register (RW,32,0x00000000)*/
#define SDMD (DCR_BASE+0x0C) /* SDRAM Mode Setup register (RW,32,0x00000001) */
#define DCMD (DCR_BASE+0x10) /* DRAM Command register (RW,32,0x00000000) */
#define RFSH0 (DCR_BASE+0x14) /* DRAM Refresh Cycle register 0 (RW,32,0x00000000) */
#define PDWC (DCR_BASE+0x18) /* Power Down Mode control register (RW,32,0x00000003) */
#define RFSH1 (DCR_BASE+0x1C) /* DRAM Refresh Cycle register 1 (RW,32,0x00000000) */
/* bit field of DBWC register */
#define DBWC_DBDRAM0 (0x00000000) /* DRAM disable */
#define DBWC_DBDRAM8 (0x00000001) /* 8bit width */
#define DBWC_DBDRAM16 (0x00000002) /* 16bit width */
/* bit field of DRMC register */
#define DRMC_8bit (0x00000000) /* DRAM column length : 8bit */
#define DRMC_9bit (0x00000001) /* DRAM column length : 9bit */
#define DRMC_10bit (0x00000002) /* DRAM column length : 10bit */
#define DRMC_SDRAM (0x00000000) /* DRAM architecture : SDRAM */
#define DRMC_EDO (0x00000004) /* DRAM architecture : EDO-DRAM */
#define DRMC_2CLK (0x00000000) /* SDRAM pre-charge latency : 2clock */
#define DRMC_CAS (0x00000010) /* SDRAM pre-charge latency : same as CAS latency */
#define DRMC_PD_DIS (0x00000000) /* automatic shift to SDRAM power down mode : disable */
#define DRMC_PD_EN (0x00000040) /* automatic shift to SDRAM power down mode : enable */
#define DRMC_CBR_STOP (0x00000000) /* CBR refresh : stop */
#define DRMC_CBR_EXE (0x00000080) /* CBR refresh : execution */
/* bit field of DRPC register */
#define DRPC_DRAMSPEC (0x0000000F) /* DRAMSPEC[3:0] */
/* bit field of SDMD register */
#define SDMD_CL2 (0x00000000) /* SDRAM CAS latency : 2 */
#define SDMD_CL3 (0x00000001) /* SDRAM CAS latency : 3 */
#define SDMD_MODEWR (0x00000080) /* setting operation : valid */
/* bit field of DCMD register */
#define DCMD_S_NOP (0x00000000) /* No operation */
#define DCMD_S_PALL (0x00000004) /* SDRAM all bank pre-charge command */
#define DCMD_S_REF (0x00000005) /* SDRAM CBR refresh command */
#define DCMD_S_SELF (0x00000006) /* SDRAM self refresh start command */
#define DCMD_S_SREX (0x00000007) /* SDRAM self refresh stop command */
#define DCMD_EDO_NOP (0x00000000) /* No operation */
#define DCMD_EDO_PC (0x00000004) /* EDO-DRAM pre-charge cycle */
#define DCMD_EDO_REF (0x00000005) /* EDO-DRAM CBR refresh cycle */
#define DCMD_EDO_SELF (0x00000006) /* EDO-DRAM self refresh start cycle */
#define DCMD_EDO_SREX (0x00000007) /* EDO-DRAM self refresh stop cycle */
/* bit field of RFSH0 register */
#define RFSH0_RCCON (0x00000001) /* RCCON bit, refresh frequency = refclk(RFSH1)*2(RCCON=0) */
#define RFSH0_SINGLE (0x00000000) /* RCCON bit, refresh frequency = refclk(RFSH1) (RCCON=1) */
/* bit field of RFSH1 register */
#define RFSH1_RFSEL1 (0x000007FF) /* RFSEL1[10:0], refckl(RFSH1) = CCLK/RFSEL1[10:0] */
/* bit field of PDWC register */
#define PDWC_1 (0x00000000) /* when 1 or more cycles of idol state continue,
it shifts to power down mode. */
#define PDWC_2 (0x00000001) /* : */
#define PDWC_3 (0x00000002) /* : */
#define PDWC_4 (0x00000003) /* : */
#define PDWC_5 (0x00000004) /* : */
#define PDWC_6 (0x00000005) /* : */
#define PDWC_7 (0x00000006) /* : */
#define PDWC_8 (0x00000007) /* : */
#define PDWC_9 (0x00000008) /* : */
#define PDWC_10 (0x00000009) /* : */
#define PDWC_11 (0x0000000A) /* : */
#define PDWC_12 (0x0000000B) /* : */
#define PDWC_13 (0x0000000C) /* : */
#define PDWC_14 (0x0000000D) /* : */
#define PDWC_15 (0x0000000E) /* : */
#define PDWC_16 (0x0000000F) /* when 16 or more cycles of idol state continue,
it shifts to power down mode. */
/*****************************************************/
/* DMA control register */
/*****************************************************/
#define DMA_BASE (0x7BE00000) /* base address */
#define DMAMOD (DMA_BASE+0x0000) /* DMA Mode register (RW,32,0x00000000) */
#define DMASTA (DMA_BASE+0x0004) /* DMA Status register (R,32,0x00000000) */
#define DMAINT (DMA_BASE+0x0008) /* DMA interrupt Status register (R,32,0x00000000) */
#define DMACMSK0 (DMA_BASE+0x0100) /* Channel 0 Mask register (RW,32,0x00000001) */
#define DMACTMOD0 (DMA_BASE+0x0104) /* Channel 0 Transfer Mode register (RW,32,0x00000040) */
#define DMACSAD0 (DMA_BASE+0x0108) /* Channel 0 Source Address register (RW,32,0x00000000) */
#define DMACDAD0 (DMA_BASE+0x010C) /* Channel 0 Destination Address register (RW,32,0x00000000) */
#define DMACSIZ0 (DMA_BASE+0x0110) /* Channel 0 Transfer Size register (RW,32,0x00000000) */
#define DMACCINT0 (DMA_BASE+0x0114) /* Channel 0 interrupt Clear register (W,32,--) */
#define DMACMSK1 (DMA_BASE+0x0200) /* Channel 1 Mask register (RW,32,0x00000001) */
#define DMACTMOD1 (DMA_BASE+0x0204) /* Channel 1 Transfer Mode register (RW,32,0x00000040) */
#define DMACSAD1 (DMA_BASE+0x0208) /* Channel 1 Source Address register (RW,32,0x00000000) */
#define DMACDAD1 (DMA_BASE+0x020C) /* Channel 1 Destination Address register (RW,32,0x00000000) */
#define DMACSIZ1 (DMA_BASE+0x0210) /* Channel 1 Transfer Size register (RW,32,0x00000000) */
#define DMACCINT1 (DMA_BASE+0x0214) /* Channel 1 interrupt Clear register (W,32,--) */
#define DMACMSK2 (DMA_BASE+0x0300) /* Channel 2 Mask register (RW,32,0x00000001) */
#define DMACTMOD2 (DMA_BASE+0x0304) /* Channel 2 Transfer Mode register (RW,32,0x00000040) */
#define DMACSAD2 (DMA_BASE+0x0308) /* Channel 2 Source Address register (RW,32,0x00000000) */
#define DMACDAD2 (DMA_BASE+0x030C) /* Channel 2 Destination Address register (RW,32,0x00000000) */
#define DMACSIZ2 (DMA_BASE+0x0310) /* Channel 2 Transfer Size register (RW,32,0x00000000) */
#define DMACCINT2 (DMA_BASE+0x0314) /* Channel 2 interrupt Clear register (W,32,--) */
#define DMACMSK3 (DMA_BASE+0x0400) /* Channel 3 Mask register (RW,32,0x00000001) */
#define DMACTMOD3 (DMA_BASE+0x0404) /* Channel 3 Transfer Mode register (RW,32,0x00000040) */
#define DMACSAD3 (DMA_BASE+0x0408) /* Channel 3 Source Address register (RW,32,0x00000000) */
#define DMACDAD3 (DMA_BASE+0x040C) /* Channel 3 Destination Address register (RW,32,0x00000000) */
#define DMACSIZ3 (DMA_BASE+0x0410) /* Channel 3 Transfer Size register (RW,32,0x00000000) */
#define DMACCINT3 (DMA_BASE+0x0414) /* Channel 3 interrupt Clear register (W,32,--) */
/* bit field of DMAMOD register */
#define DMAMOD_PRI (0x00000001) /* PRI bit */
#define DMAMOD_FIX (0x00000000) /* Priority of DMA channel : CH0 > CH1 */
#define DMAMOD_RR (0x00000001) /* Priority of DMA channel : Round robin */
/* bit field of DMASTA register */
#define DMASTA_STA0 (0x00000001) /* Non-transmitted data is in CH0 */
#define DMASTA_STA1 (0x00000002) /* Non-transmitted data is in CH1 */
/* bit field of DMAINT register */
#define DMAINT_IREQ0 (0x00000001) /* CH0 interrupt */
#define DMAINT_IREQ1 (0x00000002) /* CH1 interrupt */
#define DMAINT_ISTA0 (0x00000100) /* CH0 abnormal end */
#define DMAINT_ISTA1 (0x00000200) /* CH1 abnormal end */
#define DMAINT_ISTP0 (0x00010000) /* CH0 abnormal end situation */
#define DMAINT_ISTP1 (0x00020000) /* CH1 abnormal end situation */
/* bit field of DMAMSK0,1 register */
#define DMACMSK_MSK (0x00000001) /* Mask */
/* bit field of DMATMOD0,1 register */
#define DMACTMOD_ARQ (0x00000001) /* Auto request */
#define DMACTMOD_ERQ (0x00000000) /* External request */
#define DMACTMOD_BYTE (0x00000000) /* Byte transmission */
#define DMACTMOD_HWORD (0x00000002) /* Half word transmission */
#define DMACTMOD_WORD (0x00000004) /* Word transmission */
#define DMACTMOD_SFA (0x00000000) /* Source data type(fixed address device) */
#define DMACTMOD_SIA (0x00000008) /* Source data type(incremental address device) */
#define DMACTMOD_DFA (0x00000000) /* Destination data type(fixed address device) */
#define DMACTMOD_DIA (0x00000010) /* Destination data type(incremental address device) */
#define DMACTMOD_BM (0x00000000) /* Bus request mode(burst mode) */
#define DMACTMOD_CSM (0x00000020) /* Bus request mode(cycle steal mode) */
#define DMACTMOD_IMK (0x00000040) /* interrupt mask */
/*****************************************************/
/* port control register */
/*****************************************************/
#define PCR_BASE (0xB7A00000) /* base address */
#define GPPOA (PCR_BASE+0x00) /* port A output register (RW,16,--) */
#define GPPIA (PCR_BASE+0x04) /* port A input register (R,16,--)*/
#define GPPMA (PCR_BASE+0x08) /* port A Mode register (RW,16,0x0000) */
#define GPPOB (PCR_BASE+0x20) /* port B Output register (RW,16,--) */
#define GPPIB (PCR_BASE+0x24) /* port B Input register (R,16,--) */
#define GPPMB (PCR_BASE+0x28) /* port B Mode register (RW,16,0x0000) */
#define GPPOC (PCR_BASE+0x40) /* port C Output register (RW,16,--) */
#define GPPIC (PCR_BASE+0x44) /* port C Input register (R,16,--) */
#define GPPMC (PCR_BASE+0x48) /* port C Mode register (RW,16,0x0000) */
#define GPPOD (PCR_BASE+0x60) /* port D Output register (RW,16,--) */
#define GPPID (PCR_BASE+0x64) /* port D Input register (R,16,--) */
#define GPPMD (PCR_BASE+0x68) /* port D Mode register (RW,16,0x0000) */
#define GPPOE (PCR_BASE+0x80) /* port E Output register (RW,16,--) */
#define GPPIE (PCR_BASE+0x84) /* port E Input register (R,16,--) */
#define GPPME (PCR_BASE+0x88) /* port E Mode register (RW,16,0x0000) */
#define GPIEE (PCR_BASE+0x8C) /* port E interrupt enable (RW,16,0x0000) */
#define GPIPE (PCR_BASE+0x90) /* port E interrupt Polarity (RW,16,0x0000) */
#define GPISE (PCR_BASE+0x94) /* port E interrupt Status (RW,16,0x0000) */
#define GPIME (PCR_BASE+0x98) /* port E interrupt Mode register (RW,16,0x0000) */
#define GPPOF (PCR_BASE+0xA0) /* port D Output register (RW,7,--) */
#define GPPIF (PCR_BASE+0xA4) /* port D Input register (R,7,--) */
#define GPPMF (PCR_BASE+0xA8) /* port D Mode register (RW,7,0x0000) */
/* bit field of GPPOA/GPPOB/GPPOC/GPPOD/GPPOE register */
#define GPPOA_GPPOA (0xFFFF) /* GPPOA[15:0] */
#define GPPOB_GPPOB (0xFFFF) /* GPPOB[15:0] */
#define GPPOC_GPPOC (0xFFFF) /* GPPOC[15:0] */
#define GPPOD_GPPOD (0xFFFF) /* GPPOD[15:0] */
#define GPPOE_GPPOE (0xFFFF) /* GPPOE[15:0] */
#define GPPOF_GPPOF (0x007F) /* GPPOF[ 6:0] */
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