📄 ml69q6203.h
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/******************************************************************************
Copyright (C) 2005 Oki Electric Industry Co.,LTD.
System Name : ML69Q6203 CPU Board
Module Name : definition for registers
File Name : ML69Q6203.h
Revision : 01.00
Date : 2005/03/03 First version
******************************************************************************/
#ifndef ML69Q6203_H
#define ML69Q6203_H
#ifdef __cplusplus
extern "C" {
#endif
/*****************************************************/
/* system control register */
/*****************************************************/
#define SCR_BASE (0xB8000000) /* base address */
#define IDR (SCR_BASE+0x00) /* type and revision (RO,32,0x00000100) */
#define CLKSTP (SCR_BASE+0x04) /* clock stop register (W,32,0x00000000) */
#define CGBCNT0 (SCR_BASE+0x08) /* clock(CGB) control register 0 (RW,32,0x00000000) */
#define CKWT (SCR_BASE+0x0C) /* clock wait register (RW,32,0x000000FF) */
#define RMPCON (SCR_BASE+0x10) /* remap control register (RW,32,0x00000000) */
#define CGBCNT1 (SCR_BASE+0x18) /* clock(CGB) control register 1 (RW,32,0x00000000) */
#define CGBCNT2 (SCR_BASE+0x1C) /* clock(CGB) control register 2 (RW,32,0x00000000) */
/* for IDR, CLKSTP, CGBCNT0, CKWT, RMPCON, CGBCNT1, CGBCNT2 registers */
#define SCR_UNLOCK 0x0000003c
/* bit field of CLKSTP register */
#define CLKSTP_SIO (0x00000001) /* SIO HALT */
#define CLKSTP_TIC (0x00000002) /* TIC HALT */
#define CLKSTP_HALT (0x00000004) /* CPU group HALT */
#define CLKSTP_STOP (0x00000080) /* STOPMODE */
/* bit field of CGBCNT0 register */
#define CGBCNT0_FCLKGEAR1 (0x00000000) /* CPUCLK 1 dividing : 120 MHz */
#define CGBCNT0_FCLKGEAR2 (0x00000001) /* CPUCLK 2 dividing : 60 MHz */
#define CGBCNT0_FCLKGEAR4 (0x00000002) /* CPUCLK 4 dividing : 30 MHz */
#define CGBCNT0_FCLKGEAR8 (0x00000003) /* CPUCLK 8 dividing : 15 MHz */
#define CGBCNT0_FCLKGEAR16 (0x00000004) /* CPUCLK 16 dividing : 7.5 MHz */
#define CGBCNT0_FCLKGEAR32 (0x00000005) /* CPUCLK 32 dividing : 3.75 MHz */
#define CGBCNT0_FCLKGEAR32K (0x00000007) /* CPUCLK 32 kHz */
/* bit field of CGBCNT0 register */
#define CGBCNT0_HCLKGEAR1 (0x00000000) /* CPUCLK/1 dividing : 120 MHz */
#define CGBCNT0_HCLKGEAR2 (0x00000008) /* CPUCLK/1 dividing : 120 MHz */
#define CGBCNT0_HCLKGEAR4 (0x00000080) /* CPUCLK/2 dividing : 60 MHz */
#define CGBCNT0_HCLKGEAR8 (0x00000088) /* CPUCLK/4 dividing : 30 MHz */
/* bit field of CGBCNT0 register */
#define CGBCNT0_CCLKGEAR1 (0x00000000) /* CPUCLK/1 dividing : 120 MHz */
#define CGBCNT0_CCLKGEAR32K (0x00000070) /* CPUCLK 32 kHz */
/* bit field of RMPCON register */
#define RMPCON_ENABLE (0x00000008) /* remap enabled */
#define RMPCON_DISABLE (0x00000000) /* remap disabled */
#define RMPCON_EXT (0x00000000) /* device space is external SRAM */
#define RMPCON_DRAM (0x00000001) /* device space is external SDRAM */
#define RMPCON_AHB (0x00000002) /* device space is AHBRAM*/
/*****************************************************************************
CONFIG
*****************************************************************************/
#define CNFIG_BAS 0x80000000
#define PDMASK (CNFIG_BAS+(0x00)) /* power down mask register (RW,32,0x00000000) */
#define MCKST (CNFIG_BAS+(0x04)) /* dodule clock stop register (RW,32,0x00000000) */
#define PIOCTL (CNFIG_BAS+(0x08)) /* chabge PIO function register (RW,32,0x00000000) */
#define I2SCNTL (CNFIG_BAS+(0x0C)) /* I2S control register (RW,32,0x00000000) */
#define OCONFIG (CNFIG_BAS+(0x10)) /* other configuration register (RW,32,0x00000000) */
#define TST (CNFIG_BAS+(0x14)) /* ATD test register (RW,32,0x00000000) */
/* for MCKST, PIOCTL, I2SCNTL, OCONFIG, TST registers */
#define CNFIG_UNLOCK 0x0000003c
/* bit field of PDMASK */
#define PDMASK_PDMASK_EN (0x0000) /* power cut without RTC disable */
#define PDMASK_PDMASK_DIS (0x0001) /* power cut without RTC disable */
/* these are aliases */
#define PDMASK_RTC_DIS (0x0000) /* RTC disabled, can powerdown */
#define PDMASK_RTC_EN (0x0001) /* RTC enabled, can NOT powerdown */
/* bit field of MCKST */
#define MCKST_DMAC_EN (0x0000) /* supply DMAC clock to enable */
#define MCKST_DMAC_DIS (0x0001) /* supply DMAC clock to disable */
#define MCKST_DRAMC_EN (0x0000) /* supply DRAMC clock to enable */
#define MCKST_DRAMC_DIS (0x0002) /* supply DRAMC clock to disable */
#define MCKST_I2SSEND_EN (0x0000) /* supply I2S send clock enable */
#define MCKST_I2SSEND_DIS (0x0004) /* supply I2S send clock disable */
#define MCKST_I2SSRCV_EN (0x0000) /* supply I2S receive clock enable */
#define MCKST_I2SSRCV_DIS (0x0008) /* supply I2S receive clock disable */
#define MCKST_NFC_EN (0x0000) /* supply clock to NAND FLASH controller enable */
#define MCKST_NFC_DIS (0x0010) /* supply clock to NAND FLASH controller disable */
#define MCKST_NFB_EN (0x0000) /* supply clock to NAND FLASH Buffer memory enable */
#define MCKST_NFB_DIS (0x0020) /* supply clock to NAND FLASH Buffer memory disable */
#define MCKST_XSYSCLK_DIS (0x0000) /* supply clock to XSYSCLK disable */
#define MCKST_XSYSCLK_EN (0x0040) /* supply clock to XSYSCLK enable */
/*****************************************************/
/* interrupt control register */
/*****************************************************/
#define ICR_BASE (0x78000000) /* base address of interrupt control register */
#define IRQ (ICR_BASE+0x00) /* IRQ register (R,32,0x00000000) */
#define IRQS (ICR_BASE+0x04) /* IRQ soft register (RW,32,0x00000000) */
#define FIQ (ICR_BASE+0x08) /* FIQ register (R,32,0x00000000) */
#define FIQRAW (ICR_BASE+0x0C) /* FIQRAW status register (R,32,--)*/
#define FIQEN (ICR_BASE+0x10) /* FIQ enable register (RW,32,0x00000000)*/
#define IRN (ICR_BASE+0x14) /* IRQ number register (R,32,0x00000000)*/
#define CIL (ICR_BASE+0x18) /* current IRQ level register (RW,32,0x00000000)*/
#define ILC0 (ICR_BASE+0x20) /* IRQ level control register 0 (RW,32,0x00000000) */
#define ILC1 (ICR_BASE+0x24) /* IRQ level control register 1 (RW,32,0x00000000) */
#define CILCL (ICR_BASE+0x28) /* current IRQ level clear register (W,32,--) */
#define CILE (ICR_BASE+0x2C) /* current IRQ level encode register (R,32,0x00000000) */
#define EIC_BASE (0x7BF00000) /* base address */
#define IRCL (EIC_BASE+0x04) /* Extended interrupt Clear register (W,32,--) */
#define IRQA (EIC_BASE+0x10) /* Extended interrupt IRQ register (RW,32,0x00000000) */
#define IDM (EIC_BASE+0x14) /* Extended interrupt Mode control register (RW,32,0x00000000) */
#define ILC (EIC_BASE+0x18) /* Extended interrupt IRQ Level control register (RW,32,0x00000000) */
/* bit field of IRQ register */
#define IRQ_nIR0 (0x00000001) /* nIR[0] */
#define IRQ_nIR1 (0x00000002) /* nIR[1] */
#define IRQ_nIR2 (0x00000004) /* nIR[2] */
#define IRQ_nIR3 (0x00000008) /* nIR[3] */
#define IRQ_nIR4 (0x00000010) /* nIR[4] */
#define IRQ_nIR5 (0x00000020) /* nIR[5] */
#define IRQ_nIR6 (0x00000040) /* nIR[6] */
#define IRQ_nIR7 (0x00000080) /* nIR[7] */
#define IRQ_nIR8 (0x00000100) /* nIR[8] */
#define IRQ_nIR9 (0x00000200) /* nIR[9] */
#define IRQ_nIR10 (0x00000400) /* nIR[10] */
#define IRQ_nIR11 (0x00000800) /* nIR[11] */
#define IRQ_nIR12 (0x00001000) /* nIR[12] */
#define IRQ_nIR13 (0x00002000) /* nIR[13] */
#define IRQ_nIR14 (0x00004000) /* nIR[14] */
#define IRQ_nIR15 (0x00008000) /* nIR[15] */
/* bit field of IRQS register */
#define IRQS_IRQS (0x00000002) /* IRQS bit */
/* bit field of FIQ register */
#define FIQ_FIQ (0x00000001) /* FIQ bit */
/* bit field of FIQRAW register */
#define FIQRAW_FIQRAW (0x00000001) /* FIQRAW bit */
/* bit field of FIQEN register */
#define FIQEN_FIQEN (0x00000001) /* FIQEN bit */
/* bit field of IRN register */
#define IRN_IRN (0x0000007F) /* IRN[6:0] */
/* bit field of CIL register */
#define CIL_INT_LV1 (0x00000002) /* interrupt level 1 */
#define CIL_INT_LV2 (0x00000004) /* interrupt level 2 */
#define CIL_INT_LV3 (0x00000008) /* interrupt level 3 */
#define CIL_INT_LV4 (0x00000010) /* interrupt level 4 */
#define CIL_INT_LV5 (0x00000020) /* interrupt level 5 */
#define CIL_INT_LV6 (0x00000040) /* interrupt level 6 */
#define CIL_INT_LV7 (0x00000080) /* interrupt level 7 */
/* bit field of ILC0 register */
#define ILC0_ILR0 (0x00000007) /* nIR[0] */
#define ILC0_ILR1 (0x00000070) /* nIR[1],nIR[2],nIR[3] */
#define ILC0_ILR4 (0x00070000) /* nIR[4],nIR[5] */
#define ILC0_ILR6 (0x07000000) /* nIR[6],nIR[7] */
#define ILC0_INT_LV1 (0x11111111) /* interrupt level 1 */
#define ILC0_INT_LV2 (0x22222222) /* interrupt level 2 */
#define ILC0_INT_LV3 (0x33333333) /* interrupt level 3 */
#define ILC0_INT_LV4 (0x44444444) /* interrupt level 4 */
#define ILC0_INT_LV5 (0x55555555) /* interrupt level 5 */
#define ILC0_INT_LV6 (0x66666666) /* interrupt level 6 */
#define ILC0_INT_LV7 (0x77777777) /* interrupt level 7 */
/* bit field of ILC1 register */
#define ILC1_ILR8 (0x00000007) /* nIR[8] */
#define ILC1_ILR9 (0x00000070) /* nIR[9] */
#define ILC1_ILR10 (0x00000700) /* nIR[10] */
#define ILC1_ILR11 (0x00007000) /* nIR[11] */
#define ILC1_ILR12 (0x00070000) /* nIR[12] */
#define ILC1_ILR13 (0x00700000) /* nIR[13] */
#define ILC1_ILR14 (0x07000000) /* nIR[14] */
#define ILC1_ILR15 (0x70000000) /* nIR[15] */
#define ILC1_INT_LV1 (0x11111111) /* interrupt level 1 */
#define ILC1_INT_LV2 (0x22222222) /* interrupt level 2 */
#define ILC1_INT_LV3 (0x33333333) /* interrupt level 3 */
#define ILC1_INT_LV4 (0x44444444) /* interrupt level 4 */
#define ILC1_INT_LV5 (0x55555555) /* interrupt level 5 */
#define ILC1_INT_LV6 (0x66666666) /* interrupt level 6 */
#define ILC1_INT_LV7 (0x77777777) /* interrupt level 7 */
/* bit field of CILCL register */
#define CILCL_CLEAR (0x00000001) /* most significant '1' bit of CIL is cleared */
/* bit field of CILE register */
#define CILE_CILE (0x00000007) /* CILE[2:0] */
/* bit field of IRCL register */
#define IRCL_IRCL (0x0000007F) /* IRCL[6:0] */
/* bit field of IRQA register */
#define IRQA_IRQ16 (0x00000001) /* IRQ16 */
#define IRQA_IRQ17 (0x00000002) /* IRQ17 */
#define IRQA_IRQ18 (0x00000004) /* IRQ18 */
#define IRQA_IRQ19 (0x00000008) /* IRQ19 */
#define IRQA_IRQ20 (0x00000010) /* IRQ20 */
#define IRQA_IRQ21 (0x00000020) /* IRQ21 */
#define IRQA_IRQ22 (0x00000040) /* IRQ22 */
#define IRQA_IRQ23 (0x00000080) /* IRQ23 */
#define IRQA_IRQ24 (0x00000100) /* IRQ24 */
#define IRQA_IRQ25 (0x00000200) /* IRQ25 */
#define IRQA_IRQ26 (0x00000400) /* IRQ26 */
#define IRQA_IRQ27 (0x00000800) /* IRQ27 */
#define IRQA_IRQ28 (0x00001000) /* IRQ28 */
#define IRQA_IRQ29 (0x00002000) /* IRQ29 */
#define IRQA_IRQ30 (0x00004000) /* IRQ30 */
#define IRQA_IRQ31 (0x00008000) /* IRQ31 */
/* bit field of IDM register */
#define IDM_IDM22 (0x00000040) /* IRQ22 */
#define IDM_IDM26 (0x00000400) /* IRQ26 */
#define IDM_IDM28 (0x00001000) /* IRQ28 */
#define IDM_IDM30 (0x00004000) /* IRQ31 */
#define IDM_IDMP22 (0x00000080) /* IRQ22 */
#define IDM_IDMP26 (0x00000800) /* IRQ26 */
#define IDM_IDMP28 (0x00002000) /* IRQ28 */
#define IDM_IDMP30 (0x00008000) /* IRQ31 */
#define IDM_INT_L_L (0x00000000) /* level sensing, interrupt occurs when 'L' */
#define IDM_INT_L_H (0x0000AAAA) /* level sensing, interrupt occurs when 'H' */
#define IDM_INT_E_F (0x00005555) /* edge sensing, interrupt occurs when falling edge */
#define IDM_INT_E_R (0x0000FFFF) /* edge sensing, interrupt occurs when rising edge */
#define IDM_IRQ22 (0x000000C0) /* IRQ22 */
#define IDM_IRQ26 (0x00000C00) /* IRQ26 */
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