cstartup_iar_ml69.s

来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· S 代码 · 共 267 行

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Part one of the system initialization code,
;; contains low-level
;; initialization.
;;
;; Copyright 2006 IAR Systems. All rights reserved.
;;
;; $Revision: 14941 $
;;

        MODULE  ?cstartup

        ;; Forward declaration of sections.
        SECTION IRQ_STACK:DATA:NOROOT(3)
        SECTION CSTACK:DATA:NOROOT(3)
	      SECTION SVC_STACK:DATA:NOROOT(3)

;
; The module in this file are included in the libraries, and may be
; replaced by any user-defined modules that define the PUBLIC symbol
; __iar_program_start or a user defined start symbol.
;
; To override the cstartup defined in the library, simply add your
; modified version to the workbench project.

        SECTION .intvec:CODE:NOROOT(2)

        PUBLIC  __vector                 
        PUBLIC  __iar_program_start
        EXTERN irq_handler
        
        ARM
__vector:
        ;;
        ldr   pc,[pc,#+24]              ;; Reset
        B   .                           ;; Undefined instructions
        B   .                           ;; Software interrupt (SWI/SVC)
        B   .            		            ;; Prefetch abort
        B   .			                      ;; Data abort
        DC32  0                         ;; RESERVED
        ldr   pc,[pc,#+24]              ;; IRQ
        B   .                           ;; FIQ

        DC32  __iar_program_start       ;; Reset
        DC32  0                         ;; Undefined instructions
        DC32  0                         ;; Software interrupt (SWI/SVC)
        DC32  0                         ;; Prefetch abort
        DC32  0                         ;; Data abort
        DC32  0                         ;; RESERVED
        DC32  irq_handler               ;; IRQ
        DC32  0                         ;; FIQ


; --------------------------------------------------
; ?cstartup -- low-level system initialization code.
;
; After a reser execution starts here, the mode is ARM, supervisor
; with interrupts disabled.
;



        SECTION .text:CODE:NOROOT(2)

;        PUBLIC  ?cstartup
        EXTERN  ?main
        REQUIRE __vector

        ARM

__iar_program_start:
?cstartup:

;
; Add initialization needed before setup of stackpointers here.
;
BIC_BASE        DEFINE  0x78100000; address of BIC base
DRAMC_BASE      DEFINE  0x78180000; address of DRAMC base	

	      BL      setup_ex_sram_rom
	      BL      setup_ex_dram
        BL      setup_protection_unit_cache

;
; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS.
; The stack segments must be defined in the linker command file,
; and be declared above.
;
; --------------------
; Mode, correspords to bits 0-5 in CPSR
MODE_BITS	DEFINE	0x1F		; Bit mask for mode bits in CPSR
USR_MODE	DEFINE	0x10		; User mode
FIQ_MODE	DEFINE	0x11		; Fast Interrupt Request mode
IRQ_MODE	DEFINE	0x12		; Interrupt Request mode
SVC_MODE	DEFINE	0x13		; Supervisor mode
ABT_MODE	DEFINE	0x17		; Abort mode
UND_MODE	DEFINE	0x1B		; Undefined Instruction mode
SYS_MODE	DEFINE	0x1F		; System mode


        MRS     r0, cpsr                ; Original PSR value

        BIC     r0, r0, #MODE_BITS       ; Clear the mode bits
        ORR     r0, r0, #IRQ_MODE       ; Set IRQ mode bits
        MSR     cpsr_c, r0              ; Change the mode
        LDR     sp, =SFE(IRQ_STACK)     ; End of IRQ_STACK

        BIC     r0, r0, #MODE_BITS       ; Clear the mode bits
        ORR     r0, r0, #SVC_MODE       ; Set SVC mode bits
        MSR     cpsr_c, r0              ; Change the mode
        LDR     sp, =SFE(SVC_STACK)     ; End of SVC_STACK
        
        BIC     r0 ,r0, #MODE_BITS       ; Clear the mode bits
        ORR     r0 ,r0, #SYS_MODE       ; Set System mode bits
        MSR     cpsr_c, r0              ; Change the mode
        LDR     sp, =SFE(CSTACK)        ; End of CSTACK

#ifdef __ARMVFP__
        ;; Enable the VFP coprocessor.

        MOV     r0, #0x40000000         ; Set EN bit in VFP
        FMXR    fpexc, r0               ; FPEXC, clear others.

;
; Disable underflow exceptions by setting flush to zero mode.
; For full IEEE 754 underflow compliance this code should be removed
; and the appropriate exception handler installed.
;

        MOV     r0, #0x01000000         ; Set FZ bit in VFP
        FMXR    fpscr, r0               ; FPSCR, clear others.
#endif

;
; Add more initialization here
;
; Continue to ?main for more IAR specific system startup

                ldr     r0,=?main
                bx      r0

;:*************************************************************************************************
;; Setup external SRAM/ROM                                                                        *
;;*************************************************************************************************
setup_ex_sram_rom
        LDR     R0, =BIC_BASE
        ;; setup BWC register(ROM:16bit,RAM:16bit)
        MOV     R1, #0x2A8
        STR     R1, [R0, #0x0]
        ;; setup ROMAC register
        MOV     R1, #0x3
        STR     R1, [R0, #0x4]
        ;; setup RAMAC register
        MOV     R1, #0x3
        STR     R1, [R0, #0x8]

        MOV     pc, lr

;:*************************************************************************************************
;; Setup external DRAM                                                                            *
;;*************************************************************************************************
setup_ex_dram
        LDR     R0, =DRAMC_BASE
        ;; waite 200usec or more
        MOV     R1, #0x1000
wait_loop
        SUBS    R1, R1, #1
        BPL     wait_loop
        ;; DRAM bus width control register (DBWC@0x7818_0000)
        LDR     R1, =0x2        ; 16bit
        STR     R1, [R0, #0]
        ;; DRAM control register (DRMC@0x7818_0004)
        LDR     R1, =0x92       ; column:9bit, type of DRAM:SDRAM, precharge latency:3clk
        STR     R1, [R0, #0x4]  ; auto shift to power down mode:disable, CBR refresh:disable
        ;; DRAM parameter control register (DRPC@0x7818_0008)
        LDR     R1, =0x2
        STR     R1, [R0, #0x8]
        ;; RFCG register(RFCG@0x7818_001C)
        LDR     R1, =0x0075     ; select refreqa(64.10kHz : CCLK=7.5MHz)
        STR     R1, [R0, #0x1C]
        ;; DRAM refresh cycle control register(RFSH@0x7818_0014)
        LDR     R1, =0x1        ; refreqa(8usec) / 1
        STR     R1, [R0, #0x14]
        ;; DRAM power down mode control register (PDWC@0x7818_0018)
        LDR     R1, =0x3
        STR     R1, [R0, #0x18]
        ;; all bank pre-charge
        LDR     R1, =0x4        ; all bank precharge command
        STR     R1, [R0, #0x10]
        ;; CBR x 8
        LDR     R1, =0x5        ; CBR refresh command
        STR     R1, [R0, #0x10]
        STR     R1, [R0, #0x10]
        STR     R1, [R0, #0x10]
        STR     R1, [R0, #0x10]
        STR     R1, [R0, #0x10]
        STR     R1, [R0, #0x10]
        STR     R1, [R0, #0x10]
        STR     R1, [R0, #0x10]
        ;; SDRAM mode register (SDMD@0x7818_000C)
        LDR     R1, =0x80       ; CL3
        STR     R1, [R0, #0xC]
        ;; DRAM control register (DRMC@0x7818_0004)
        LDR     R1, =0x92       ; column:9bit, type of DRAM:SDRAM, precharge latency:3clk
        STR     R1, [R0, #0x4]  ; auto shift to power down mode:disable, CBR refresh:enable

        MOV     pc, lr

;:*************************************************************************************************
;; Setup protection unit                                                                          *
;;*************************************************************************************************
setup_protection_unit_cache

	;; setup data cache
        LDR     R0, =0x1E       ; area1,2,3,4 : enable (7654:3210)
        MCR     p15, 0, R0, c2, c0, 0
        ;; setup instruction cache
        LDR     R0, =0x12       ; area1,4 : enable
        MCR     p15, 0, R0, c2, c0, 1
	
        ;; setup write buffer
        LDR     R0, =0x0C       ; area2,3 : enable
        MCR     p15, 0, R0, c3, c0, 0
	
        ;; setup data access permission
        LDR     R0, =0x00033333 ; area0,1,2,3,4 : RW/RW
        MCR     p15, 0, R0, c5, c0, 2; data access permission

	;; setup instruction access permission
        LDR     R0, =0x00033333 ; area0,1,2,3,4 : RW/RW
        MCR     p15, 0, R0, c5, c0, 3; instruction access permission

	;; setup base size(5:1), address(31:12) and enable/disable(lsb)
        LDR     R0, =0x3F       ; size : 4GB, base address : 0x00000000
        MCR     p15, 0, R0, c6, c0, 0; area0
        LDR     R0, =0x35       ; size : 128MB, base address : 0x00000000
        MCR     p15, 0, R0, c6, c1, 0; area1
        LDR     R0, =0x50000035 ; size : 128MB, base address : 0x50000000
        MCR     p15, 0, R0, c6, c2, 0; area2
        LDR     R0, =0xC0000035 ; size : 128MB, base address : 0xC0000000
        MCR     p15, 0, R0, c6, c3, 0; area3
        LDR     R0, =0xD0000035 ; size : 128MB, base address : 0xD0000000
        MCR     p15, 0, R0, c6, c4, 0; area4

	;; enable protection unit and cache
	LDR	r0, =0x107D
        MCR     p15, 0, R0, c1, c0, 0; write control register

        MOV     pc, lr


        END