iar_init_s.s

来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· S 代码 · 共 189 行

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Part one of the system initialization code,
;; contains low-level
;; initialization.
;;
;; Copyright 2006 IAR Systems. All rights reserved.
;;
;; $Revision: 14941 $
;;

        MODULE  ?cstartup

        ;; Forward declaration of sections.
        SECTION IRQ_STACK:DATA:NOROOT(3)
	      SECTION SVC_STACK:DATA:NOROOT(3)
	      SECTION FIQ_STACK:DATA:NOROOT(3)
	      SECTION CSTACK:DATA:NOROOT(3)

;
; The module in this file are included in the libraries, and may be
; replaced by any user-defined modules that define the PUBLIC symbol
; __iar_program_start or a user defined start symbol.
;
; To override the cstartup defined in the library, simply add your
; modified version to the workbench project.

        SECTION .intvec:CODE:NOROOT(2)

        PUBLIC  __vector                 
        PUBLIC  __iar_program_start
        EXTERN  swi_handler,IRQ_Handler
        
        ARM
__vector:
        ;;
        ldr   pc,[pc,#+24]              ;; Reset
        B   .                           ;; Undefined instructions
        ldr   pc,[pc,#+24]              ;; Software interrupt (SWI/SVC)
        B   .            		            ;; Prefetch abort
        B   .			                      ;; Data abort
        DC32  0                         ;; RESERVED
        ldr   pc,[pc,#+24]              ;; IRQ
        B   .                           ;; FIQ

        DC32  __iar_program_start       ;; Reset
        DC32  0                         ;; Undefined instructions
        DC32  swi_handler               ;; Software interrupt (SWI/SVC)
        DC32  0                         ;; Prefetch abort
        DC32  0                         ;; Data abort
        DC32  0                         ;; RESERVED
        DC32  IRQ_Handler               ;; IRQ
        DC32  0		                      ;; FIQ


; --------------------------------------------------
; ?cstartup -- low-level system initialization code.
;
; After a reser execution starts here, the mode is ARM, supervisor
; with interrupts disabled.
;



        SECTION .text:CODE:NOROOT(2)

;        PUBLIC  ?cstartup
        EXTERN  ?main
        REQUIRE __vector

        ARM

__iar_program_start:
?cstartup:

;
; Add initialization needed before setup of stackpointers here.
;

;clock control register
CLKCNT		DEFINE	0xb7000010		;CLKCNT register

;system timer setting
TMEN		DEFINE	0xb8001004
TMOVF		DEFINE	0xb8001010
TMRLR		DEFINE	0xb8001008
TMRCYC		DEFINE	10
RINGOSC		DEFINE	16
VALUE_OF_TMRLR	DEFINE	65536 - (TMRCYC * RINGOSC * 1000) /16
CHANGE_CLK_VALUE	DEFINE	0xfffffcff

; --- ring oscillator is srcsel?
		LDR	R0,=CLKCNT
		LDR	R1,[R0]
		AND	R1,R1,#0x300
		CMP	R1,#0x100
		BNE	_not_ringosc1
		
; --- set system timer
		MOV	R0,#0x0
		LDR	R1,=TMEN
		STR	R0,[R1]
		MOV	R0,#0x1
		LDR	R1,=TMOVF
		STR	R0,[R1]
		; set 10msec cycle
		LDR	R0,=VALUE_OF_TMRLR
		LDR	R1,=TMRLR
		STR	R0,[R1]
		; start system timer
		MOV	R0,#0x1
		LDR	R1,=TMEN
		STR	R0,[R1]

_not_ringosc1

; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS.
; The stack segments must be defined in the linker command file,
; and be declared above.
; --------------------
; Mode, correspords to bits 0-5 in CPSR
MODE_BITS	DEFINE	0x1F		; Bit mask for mode bits in CPSR
USR_MODE	DEFINE	0x10		; User mode
FIQ_MODE	DEFINE	0x11		; Fast Interrupt Request mode
IRQ_MODE	DEFINE	0x12		; Interrupt Request mode
SVC_MODE	DEFINE	0x13		; Supervisor mode
ABT_MODE	DEFINE	0x17		; Abort mode
UND_MODE	DEFINE	0x1B		; Undefined Instruction mode
SYS_MODE	DEFINE	0x1F		; System mode

        MRS     r0, cpsr                ; Original PSR value

        BIC     r0, r0, #MODE_BITS       ; Clear the mode bits
        ORR     r0, r0, #IRQ_MODE       ; Set IRQ mode bits
        MSR     cpsr_c, r0              ; Change the mode
        LDR     sp, =SFE(IRQ_STACK)     ; End of IRQ_STACK

        BIC     r0 ,r0, #MODE_BITS       ; Clear the mode bits
        ORR     r0 ,r0, #FIQ_MODE       ; Set FIQ mode bits
        MSR     cpsr_c, r0              ; Change the mode
        LDR     sp, =SFE(FIQ_STACK)        ; End of FIQ_STACK

        BIC     r0, r0, #MODE_BITS       ; Clear the mode bits
        ORR     r0, r0, #SVC_MODE       ; Set SVC mode bits
        MSR     cpsr_c, r0              ; Change the mode
        LDR     sp, =SFE(SVC_STACK)     ; End of SVC_STACK

; --- ring oscillator is srcsel?
		LDR	R0,=CLKCNT
		LDR	R1,[R0]
		AND	R1,R1,#0x300
		CMP	R1,#0x100
		BNE	_not_ringosc2

; --- timer overflow wait
_wait_ovf
		LDR	R1,=TMOVF
		LDR	R0,[R1]
		CMP	R0,#0x1
		BNE	_wait_ovf
		
; --- change to main clk from ring oscillator
		LDR	R1,=CLKCNT
		LDR	R0,[R1]
		LDR	R1,=CHANGE_CLK_VALUE
		AND	R0,R0, R1
		LDR	R1,=CLKCNT
		STR	R0,[R1]
_not_ringosc2

; Continue to ?main for more IAR specific system startup

                ldr     r0,=?main
                bx      r0

        END