📄 iar_pm674061_lib.s
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;********************************************************************************
;* Copyright (C) 2005 Oki Electric Industry Co., LTD. *
;* *
;* System Name : ML674051/ML674061 *
;* Module Name : ML674051/ML674061 power management (ARM and Thumb states) *
;* File Name : pm674061_lib.s *
;* Revision : 1.00 *
;* Date : 2005/02/16 *
;* *
;********************************************************************************
ROMAC1 EQU 0x00000007 ; clock gear 1/1
ROMAC2 EQU 0x00000003 ; clock gear 1/2
ROMAC4 EQU 0x00000003 ; clock gear 1/4
ROMAC8 EQU 0x00000002 ; clock gear 1/8
ROMAC16 EQU 0x00000001 ; clock gear 1/16
ROMAC32 EQU 0x00000000 ; clock gear 1/32
RAMAC1 EQU 0x00000007 ; clock gear 1/1
RAMAC2 EQU 0x00000003 ; clock gear 1/2
RAMAC4 EQU 0x00000003 ; clock gear 1/4
RAMAC8 EQU 0x00000002 ; clock gear 1/8
RAMAC16 EQU 0x00000001 ; clock gear 1/16
RAMAC32 EQU 0x00000000 ; clock gear 1/32
IO0AC1 EQU 0x00000000 ; clock gear 1/1
IO0AC2 EQU 0x00000000 ; clock gear 1/2
IO0AC4 EQU 0x00000000 ; clock gear 1/4
IO0AC8 EQU 0x00000000 ; clock gear 1/8
IO0AC16 EQU 0x00000000 ; clock gear 1/16
IO0AC32 EQU 0x00000000 ; clock gear 1/32
IO1AC1 EQU 0x00000000 ; clock gear 1/1
IO1AC2 EQU 0x00000000 ; clock gear 1/2
IO1AC4 EQU 0x00000000 ; clock gear 1/4
IO1AC8 EQU 0x00000000 ; clock gear 1/8
IO1AC16 EQU 0x00000000 ; clock gear 1/16
IO1AC32 EQU 0x00000000 ; clock gear 1/32
CLKSTP EQU 0xb8000004 ; CLKSTP register
CLKCNT EQU 0xb7000010 ; CLKCNT register
CLKSTPCNT EQU 0xb7000014 ; CLKSTPCNT register
FIQEN EQU 0x78000010 ; FIQEN register
ILC0 EQU 0x78000020 ; ILC0 register
ILC1 EQU 0x78000024 ; ILC1 register
EXILCA EQU 0x7BF00018 ; EXILCA register
EXILCB EQU 0x7BF00028 ; EXILCB register
EXILCC EQU 0x7BF00038 ; EXILCC register
ROMAC EQU 0x78100004 ; ROMAC register
RAMAC EQU 0x78100008 ; RAMAC register
IO0AC EQU 0x7810000C ; IO0AC register
IO1AC EQU 0x78100010 ; IO1AC register
SWI_PM_IF_RECOV EQU 0x10 ; IRQ,FIQ recover SWI number for power management
SWI_PM_IF_DIS EQU 0x11 ; IRQ,FIQ mask SWI number for power management
STOPMODE_BIT EQU 0x80 ; STOP mode bit
HALTMODE_BIT EQU 0x04 ; HALT mode bit
; for pm_stop parameter check
STOP_CHECK1 EQU 0xcfffff0f; except IRQ4-IRQ7,IRQ28-29
STOP_CHECK2 EQU 0xffe00003; except IRQ34-43,IRQ44-52
; for pm_halt parameter check
HALT_CHECK1 EQU 0x00000000; except IRQ0-31,
HALT_CHECK2 EQU 0x00000000; except IRQ32-63,
RSEG DATA_Z:DATA:NOROOT(2)
DATA
SAVE_CPSR DS32 4 ; for save CPSR register
SAVE_FIQEN DS32 4 ; for save FIQEN register
SAVE_ILC0 DS32 4 ; for save ILC0 register
SAVE_ILC1 DS32 4 ; for save ILC1 register
SAVE_EXILCA DS32 4 ; for save EXILCA register
SAVE_EXILCB DS32 4 ; for save EXILCB register
SAVE_EXILCC DS32 4 ; for save EXILCC register
rseg .text:CODE(2)
code32
; setting value for every clock gear of external ROM,SRAM,IO
; external ROM
ROMAC_VAL
DCD ROMAC1 ; clock gear 1/1
DCD ROMAC2 ; clock gear 1/2
DCD ROMAC4 ; clock gear 1/4
DCD ROMAC8 ; clock gear 1/8
DCD ROMAC16 ; clock gear 1/16
DCD ROMAC32 ; clock gear 1/32
; external SRAM
RAMAC_VAL
DCD RAMAC1 ; clock gear 1/1
DCD RAMAC2 ; clock gear 1/2
DCD RAMAC4 ; clock gear 1/4
DCD RAMAC8 ; clock gear 1/8
DCD RAMAC16 ; clock gear 1/16
DCD RAMAC32 ; clock gear 1/32
; external IO0
IO0AC_VAL
DCD IO0AC1 ; clock gear 1/1
DCD IO0AC2 ; clock gear 1/2
DCD IO0AC4 ; clock gear 1/4
DCD IO0AC8 ; clock gear 1/8
DCD IO0AC16 ; clock gear 1/16
DCD IO0AC32 ; clock gear 1/32
; external IO1
IO1AC_VAL
DCD IO1AC1 ; clock gear 1/1
DCD IO1AC2 ; clock gear 1/2
DCD IO1AC4 ; clock gear 1/4
DCD IO1AC8 ; clock gear 1/8
DCD IO1AC16 ; clock gear 1/16
DCD IO1AC32 ; clock gear 1/32
; setting value of ILC* register for every IRQ number(maximum priority)
INTMASK_VAL
; ILC0 register
DCD 0x00000007 ; 0
DCD 0x00000070 ; 1
DCD 0x00000070 ; 2
DCD 0x00000070 ; 3
DCD 0x00070000 ; 4
DCD 0x00070000 ; 5
DCD 0x07000000 ; 6
DCD 0x07000000 ; 7
; ILC1 register
DCD 0x00000007 ; 8
DCD 0x00000070 ; 9
DCD 0x00000700 ; 10
DCD 0x00007000 ; 11
DCD 0x00070000 ; 12
DCD 0x00700000 ; 13
DCD 0x07000000 ; 14
DCD 0x70000000 ; 15
; EXILCA register
DCD 0x00000007 ; 16
DCD 0x00000007 ; 17
DCD 0x00000070 ; 18
DCD 0x00000070 ; 19
DCD 0x00000700 ; 20
DCD 0x00000700 ; 21
DCD 0x00007000 ; 22
DCD 0x00007000 ; 23
DCD 0x00070000 ; 24
DCD 0x00070000 ; 25
DCD 0x00700000 ; 26
DCD 0x00700000 ; 27
DCD 0x07000000 ; 28
DCD 0x07000000 ; 29
DCD 0x70000000 ; 30
DCD 0x70000000 ; 31
INTMASK_VAL2
; EXILCB register
DCD 0x00000007 ; 32
DCD 0x00000007 ; 33
DCD 0x00000070 ; 34
DCD 0x00000070 ; 35
DCD 0x00000700 ; 36
DCD 0x00000700 ; 37
DCD 0x00007000 ; 38
DCD 0x00007000 ; 39
DCD 0x00070000 ; 40
DCD 0x00070000 ; 41
DCD 0x00700000 ; 42
DCD 0x00700000 ; 43
DCD 0x07000000 ; 44
DCD 0x07000000 ; 45
DCD 0x70000000 ; 46
DCD 0x70000000 ; 47
; EXILCC register
DCD 0x00000007 ; 48
DCD 0x00000007 ; 49
DCD 0x00000070 ; 50
DCD 0x00000070 ; 51
DCD 0x00000700 ; 52
DCD 0x00000700 ; 53
DCD 0x00007000 ; 54
DCD 0x00007000 ; 55
DCD 0x00070000 ; 56
DCD 0x00070000 ; 57
DCD 0x00700000 ; 58
DCD 0x00700000 ; 59
DCD 0x07000000 ; 60
DCD 0x07000000 ; 61
DCD 0x70000000 ; 62
DCD 0x70000000 ; 63
;************************************************************************
;* *
;* stop clock of ML674051/ML67Q4061 series(STOP mode) *
;* *
;* pm_stop *
;* *
;* input *
;* r0,r1:IRQ number to awake *
;* ML674051/ML674061 series from STANDBY mode *
;* r0: bit0 : IRQ number 0 *
;* : : *
;* bit31 : IRQ number 31 *
;* r1: bit0 : IRQ number 32 *
;* : : *
;* bit31 : IRQ number 63 *
;* *each bit is 0 = IRQ masked *
;* 1 = IRQ allowed *
;*----------------------------------------------------------------------*
;* *
;* C API name unsigned long pm_stop (unsigned long Irq_enable1, *
;* unsigned long Irq_enable2) *
;* *
;* input unsigned long Irq_enable1 *
;* unsigned long Irq_enable2 *
;* *
;* output 0 : normal end *
;* non 0 : input parameter error *
;* *
;*----------------------------------------------------------------------*
;* *
;* using registers r0,r1,r2,r3,r4,r5,r6,r7 *
;* (include registers used in STOP,HALT common routine) *
;* *
;************************************************************************
EXPORT pm_stop
pm_stop ; unsigned long pm_stby(unsigned long Irq_enable)
;*** save registers ***
STMFD SP!,{r2-r7,lr} ; save r2-r7,lr register
;*** set input parameter of STOP,HALT common routine
LDR r2,=STOP_CHECK1
LDR r3,=STOP_CHECK2
LDR r7,=STOPMODE_BIT
B pm_stop_halt ; branch to STOP,HALT common routine
;************************************************************************
;* *
;* stop clock of ML674051/ML67Q4061 series(HALT mode) *
;* *
;* pm_halt *
;* *
;* input *
;* r0,r1:IRQ number to awake *
;* ML674051/ML674061 series from HALT mode *
;* r0: bit0 : IRQ number 0 *
;* : : *
;* bit31 : IRQ number 31 *
;* r1: bit0 : IRQ number 32 *
;* : : *
;* bit31 : IRQ number 63 *
;* *each bit is 0 = IRQ masked *
;* 1 = IRQ allowed *
;*----------------------------------------------------------------------*
;* *
;* C API name unsigned long pm_halt (unsigned long Irq_enable1, *
;* unsigned long Irq_enable2) *
;* *
;* input unsigned long Irq_enable *
;* *
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