ml675050.h

最新版IAR FOR ARM（EWARM）5.11中的代码例子

/*****************************************************/
/*    Standby Control Register                       */
/*****************************************************/
#define SBCR_BASE       0xB6400000              /* base address of Standby Control Register */
#define MASK            (SBCR_BASE +0x00)       /* Mask status register */
#define INTPC           (SBCR_BASE +0x04)       /* Core resume condition register */
#define SDRAMCKE        (SBCR_BASE +0x08)       /* SDRAM-CKE control register */
#define PLCLR           (SBCR_BASE +0x0C)       /* Core resume input latch clear register */
#define INTPCS          (SBCR_BASE +0x10)       /* Core resume input status latch register */
#define RESUMEIN        (SBCR_BASE +0x14)       /* Core resume input status register */
#define STBCS           (SBCR_BASE +0x18)       /* CS control register for stanby mode */

/* bit field of MASK register */
#define MASK_MASK               0x00000001

/* bit field of INTPC register */
#define INTPC_INTPC0            0x00000003      /* Resume condition depend on RESUME port */
#define INTPC_INTPC1            0x00000004      /* Resume condition depend on RTC interrupt */

/* bit field of SDRAMCKE register */
#define SDRAMCKE_SDRAMCKE       0x00000001      /* SDCKE output on stanby mode */

/* bit field of PLCLR register */
#define PLCLR_LCLR              0x00000001      /* Send reset signal for interanl power resume input latch  */

/* bit field of INTPCS register */
#define INTPCS_INTPCS0          0x00000001      /* Detect core resume input by RESUME port */
#define INTPCS_INTPCS1          0x00000002      /* Detect core resume input by RTC interrupt */

/* bit field of RESUMEIN register */
#define RESUMEIN_RESUME         0x00000001
#define RESUMEIN_RTCINT         0x00000002

/* bit field of STBCS register */
#define STBCS_ROMCSO            0x00000001      /* ROMCSN output level for standby mode */
#define STBCS_RAMCSO            0x00000002      /* RAMCSN output level for standby mode */
#define STBCS_IOCS0O            0x00000004      /* IOCS0N output level for standby mode */
#define STBCS_IOCS1O            0x00000008      /* IOCS1N output level for standby mode */
#define STBCS_ROMCSM            0x00000010      /* Enable/disable ROMCSM output */
#define STBCS_RAMCSM            0x00000020      /* Enable/disable ROMCSM output */
#define STBCS_IOCS0M            0x00000040      /* Enable/disable IOCS0N output */
#define STBCS_IOCS1M            0x00000080      /* Enable/disable ISCS1N output */


/*****************************************************/
/*    Universal Control Register                     */
/*****************************************************/
#define UVCR_BASE       0xB7000000              /* base address of Universal Control Register */
#define PECLKCNT        (UVCR_BASE+0x00)        /* Peripheral clock control register */
#define PERSTCNT        (UVCR_BASE+0x04)        /* Peripheral reset control register */
#define CLKCNT          (UVCR_BASE+0x10)        /* Clock control register */
#define CLKSTPCNT       (UVCR_BASE+0x14)        /* Clock stop control register */
#define CKWT            (UVCR_BASE+0x18)        /* Clock supply wait time control register */
#define DMAARQCNT       (UVCR_BASE+0x20)        /* DMAC-A request selection register */
#define DMABRQCNT       (UVCR_BASE+0x24)        /* DMAC-B request selection register */
#define I2CNF           (UVCR_BASE+0x28)        /* I2C input noise filter setup register */
#define AHBRAMCNT       (UVCR_BASE+0x2C)        /* AHBRAM control register */
#define FTMSEL          (UVCR_BASE+0x30)        /* FTM control register */
#define EXINTCNT        (UVCR_BASE+0x34)        /* External interrupt control register */
#define VCRSCNT         (UVCR_BASE+0x38)        /* USB VCRS control register */
#define EXDMACNT        (UVCR_BASE+0x3C)        /* External DMA control register */
#define PORTSEL1        (UVCR_BASE+0x40)        /* Port control register 1 */
#define PORTSEL2        (UVCR_BASE+0x44)        /* Port control register 2 */
#define PORTSEL3        (UVCR_BASE+0x48)        /* Port control register 3 */
#define PORTSEL4        (UVCR_BASE+0x4C)        /* Port control register 4 */

/* bit field of PECLKCNT register */
#define PECLKCNT_ADC            0x00000001      /* Control ADC clock */
#define PECLKCNT_WDT            0x00000002      /* Control WDT clock */
#define PECLKCNT_FTM            0x00000004      /* Control FTM clock  */
#define PECLKCNT_LCDC           0x00000008      /* Control LCDC clock */
#define PECLKCNT_UART0          0x00000010      /* Control UART0 clock */
#define PECLKCNT_UART1          0x00000020      /* Control UART1 clock */
#define PECLKCNT_SPI0           0x00000040      /* Control SPI0 clock */
#define PECLKCNT_SPI1           0x00000080      /* Control SPI1 clock */
#define PECLKCNT_USBdev         0x00000100      /* Control USB2.0FS device clock */
#define PECLKCNT_USBhost        0x00000200      /* Control USB2.0FS host clock */
#define PECLKCNT_I2C0           0x00000400      /* Control I2C0 clock */
#define PECLKCNT_I2C1           0x00000800      /* Control I2C1 clock */
#define PECLKCNT_SIMIF0         0x00001000      /* Control SIMIF0 clock */
#define PECLKCNT_SIMIF1         0x00002000      /* Control SIMIF1 clock */
#define PECLKCNT_EXEC           0x00004000      /* Control EXEC clock */
#define PECLKCNT_GPIO0          0x00010000      /* Control GPIO0 clock */
#define PECLKCNT_GPIO1          0x00020000      /* Control GPIO1 clock */
#define PECLKCNT_GPIO2          0x00040000      /* Control GPIO2 clock */
#define PECLKCNT_GPIO3          0x00080000      /* Control GPIO3 clock */
#define PECLKCNT_GPIO4          0x00100000      /* Control GPIO4 clock */
#define PECLKCNT_GPIO5          0x00200000      /* Control GPIO5 clock */
#define PECLKCNT_GPIO6          0x00400000      /* Control GPIO6 clock */
#define PECLKCNT_GPIO7          0x00800000      /* Control GPIO7 clock */
#define PECLKCNT_DMAC0          0x01000000      /* Control DMAC0 clock */
#define PECLKCNT_DMAC1          0x02000000      /* Control DMAC1 clock */
#define PECLKCNT_DRAMC          0x04000000      /* Control DRAMC clock */

/* bit field of PERSTCNT register */
#define PERSTCNT_ADC            0x00000001      /* Control ADC reset */
#define PERSTCNT_WDT            0x00000002      /* Control WDT reset */
#define PERSTCNT_FTM            0x00000004      /* Control FTM reset  */
#define PERSTCNT_LCDC           0x00000008      /* Control LCDC reset */
#define PERSTCNT_UART0          0x00000010      /* Control UART0 reset */
#define PERSTCNT_UART1          0x00000020      /* Control UART1 reset */
#define PERSTCNT_SPI0           0x00000040      /* Control SPI0 reset */
#define PERSTCNT_SPI1           0x00000080      /* Control SPI1 reset */
#define PERSTCNT_USBdev         0x00000100      /* Control USB2.0FS device reset */
#define PERSTCNT_USBhost        0x00000200      /* Control USB2.0FS host reset */
#define PERSTCNT_I2C0           0x00000400      /* Control I2C0 reset */
#define PERSTCNT_I2C1           0x00000800      /* Control I2C1 reset */
#define PERSTCNT_SIMIF0         0x00001000      /* Control SIMIF0 reset */
#define PERSTCNT_SIMIF1         0x00002000      /* Control SIMIF1 reset */
#define PERSTCNT_EXEC           0x00004000      /* Control EXEC reset */
#define PERSTCNT_GPIO0          0x00010000      /* Control GPIO0 reset */
#define PERSTCNT_GPIO1          0x00020000      /* Control GPIO1 reset */
#define PERSTCNT_GPIO2          0x00040000      /* Control GPIO2 reset */
#define PERSTCNT_GPIO3          0x00080000      /* Control GPIO3 reset */
#define PERSTCNT_GPIO4          0x00100000      /* Control GPIO4 reset */
#define PERSTCNT_GPIO5          0x00200000      /* Control GPIO5 reset */
#define PERSTCNT_GPIO6          0x00400000      /* Control GPIO6 reset */
#define PERSTCNT_GPIO7          0x00800000      /* Control GPIO7 reset */
#define PERSTCNT_DMAC0          0x01000000      /* Control DMAC0 reset */
#define PERSTCNT_DMAC1          0x02000000      /* Control DMAC1 reset */
#define PERSTCNT_DRAMC          0x04000000      /* Control DRAMC reset */

/* bit field of CLKCNT register */
#define CLKCNT_CLKDIV           0x00000007      /* Select PLLSEL_CLK divider */
#define CLKCNT_SYSCLKSEL        0x00000008      /* Select SYSCLK frequency */
#define CLKCNT_PLLAVCO          0x00000030      /* Select PLLA frequecncy */
#define CLKCNT_PLLSEL           0x00000080      /* Enable PLL for CPU_CLK */
#define CLKCNT_APBDIV           0x00000300      /* Select APB_CLK Divident */
#define CLKCNT_SIOCLKSEL        0x00000400      /* Select SIO clock */
#define CLKCNT_PLLENA           0x00010000      /* Enable PLLA */
#define CLKCNT_PLLENB           0x00020000      /* Enable PLLB */
#define CLKCNT_SYSCLKEN         0x00040000      /* Enable SYSCLK */
#define CLKCNT_RTCCLKEN         0x00080000      /* Enable RTCCLK */

/* bit field of CLKSTPCNT register */
#define CLKSTPCNT_PLLENA        0x00010000      /* Enable PLLA in STOP mode  */
#define CLKSTPCNT_PLLENB        0x00020000      /* Enable PLLB in STOP mode */
#define CLKSTPCNT_SYSCLKEN      0x00040000      /* Enable SYSCLK in STOP mode */
#define CLKSTPCNT_RTCCLKEN      0x00080000      /* Enable RTCCLK in STOP mode */

/* bit field of CKWT register */
#define CKWT_CKWTCMP            0x00000FFF      /* The wait time until a clock signal is stabilized */
#define CKWT_CKWTSEL            0x00008000      /* Select clock until clock signal is stabilized */

/* bit field of DMAARQCNT register */
#define DMAARQCNT_CH0SEL        0x0000001F      /* DMAC-A ch0 request signal selecter */
#define DMAARQCNT_CH1SEL        0x00001F00      /* DMAC-A ch1 request signal selecter */
#define DMAARQCNT_CH2SEL        0x001F0000      /* DMAC-A ch2 request signal selecter */
#define DMAARQCNT_CH3SEL        0x1F000000      /* DMAC-A ch3 request signal selecter */

/* bit field of DMABRQCNT register */
#define DMABRQCNT_CH0SEL        0x0000001F      /* DMAC-B ch0 request signal selecter */
#define DMABRQCNT_CH1SEL        0x00001F00      /* DMAC-B ch1 request signal selecter */

/* bit field of I2CNF register */
#define I2CNF_I2CNF0            0x00000001      /* Enable I2C noise filter ch0 */
#define I2CNF_I2CNF1            0x00000002      /* Enable I2C noise filter ch1 */

/* bit field of AHBRAMCNT register */
#define AHBRAMCNT_USBRAM        0x00000001      /* Map USB2.0 host RAM to AHMRAM */
#define AHBRAMCNT_LCDCRAM       0x00000002      /* Map LCDC RAM to AHBRAM */

/* bit field of FTMSEL register */
#define FTMSEL_FTMCLK0          0x00000001      /* FTMCLK[0] source selecter */
#define FTMSEL_FTMCLK1          0x00000004      /* FTMCLK[1] source selecter */
#define FTMSEL_FTMIN0           0x00000100      /* FTMIN[0] source selecter */
#define FTMSEL_FTMIN1           0x00000400      /* FTMIN[1] source selecter */
#define FTMSEL_FTMIN2           0x00001000      /* FTMIN[2] source selecter */
#define FTMSEL_FTMIN3           0x00004000      /* FTMIN[3] source selecter */
#define FTMSEL_FTMIN4           0x00010000      /* FTMIN[4] source selecter */
#define FTMSEL_FTMIN5           0x00040000      /* FTMIN[5] source selecter */

/* bit field of EXINTCNT register */
#define EXINTCNT_EXINT0         0x00000001
#define EXINTCNT_EXINT1         0x00000002
#define EXINTCNT_EXINT2         0x00000004
#define EXINTCNT_EXINT3         0x00000008
#define EXINTCNT_EXINT4         0x00000010
#define EXINTCNT_EXINT5         0x00000020
#define EXINTCNT_EXINT6         0x00000040

/* bit field of VCRSCNT register */
#define VCRSCNT_VCRS_Z0         0x00000001
#define VCRSCNT_VCRS_Z1         0x00000002
#define VCRSCNT_VCRS_Z2         0x00000004
#define VCRSCNT_VCRS_Z3         0x00000008
#define VCRSCNT_VCRS_Z4         0x00000010
#define VCRSCNT_VCRS_Z5         0x00000020
#define VCRSCNT_VCRS_Z6         0x00000040
#define VCRSCNT_VCRS_Z7         0x00000080

/* bit field of EXDMACNT register */
#define EXDMACNT_EXREQ0         0x00000001
#define EXDMACNT_EXACK0         0x00000002
#define EXDMACNT_EXREQ1         0x00000004
#define EXDMACNT_EXACK1         0x00000008

/* bit field of PORTSEL1 register */
#define PORTSEL1_PA0            0x00000003      /* Select PA0 port function */
#define PORTSEL1_PA1            0x0000000C      /* Select PA1 port function */
#define PORTSEL1_PA2            0x00000030      /* Select PA2 port function */
#define PORTSEL1_PA3            0x000000C0      /* Select PA3 port function */
#define PORTSEL1_PA4            0x00000300      /* Select PA4 port function */
#define PORTSEL1_PA5            0x00000C00      /* Select PA5 port function */
#define PORTSEL1_PA6            0x00003000      /* Select PA6 port function */
#define PORTSEL1_PA7            0x0000C000      /* Select PA7 port function */
#define PORTSEL1_PB0            0x00030000      /* Select PB0 port function */
#define PORTSEL1_PB1            0x000C0000      /* Select PB1 port function */
#define PORTSEL1_PB2            0x00300000      /* Select PB2 port function */
#define PORTSEL1_PB3            0x00C00000      /* Select PB3 port function */
#define PORTSEL1_PB4            0x03000000      /* Select PB4 port function */
#define PORTSEL1_PB5            0x0C000000      /* Select PB5 port function */
#define PORTSEL1_PB6            0x30000000      /* Select PB6 port function */
#define PORTSEL1_PB7            0xC0000000      /* Select PB7 port function */

/* bit field of PORTSEL2 register */
#define PORTSEL2_PC0            0x00000003      /* Select PC0 port function */
#define PORTSEL2_PC1            0x0000000C      /* Select PC1 port function */
#define PORTSEL2_PC2            0x00000030      /* Select PC2 port function */
#define PORTSEL2_PC3            0x000000C0      /* Select PC3 port function */
#define PORTSEL2_PC4            0x00000300      /* Select PC4 port function */
#define PORTSEL2_PC5            0x00000C00      /* Select PC5 port function */
#define PORTSEL2_P