ml675050.h

最新版IAR FOR ARM（EWARM）5.11中的代码例子

#define CON_LCK                 0x06000000      /* Select way to lock */
#define CON_F                   0x08000000      /* Set cache memory as load mode  */
#define CON_BNK                 0x30000000      /* Select way to load */

/* bit field of CACHE register */
#define CACHE_C10               0x00000004      /* Enable bank 10 */
#define CACHE_C24               0x00000100      /* Enable bank 24 */
#define CACHE_C25               0x00000200      /* Enable bank 25 */
#define CACHE_C26               0x00000400      /* Enable bank 26 */
#define CACHE_C27               0x00000800      /* Enable bank 27 */
#define CACHE_C28               0x00001000      /* Enable bank 28 */
#define CACHE_C29               0x00002000      /* Enable bank 29 */
#define CACHE_C0                0x00010000      /* Enable bank 0 */


/*****************************************************/
/*    USB2.0FS Host/USB2.0LS Host Control Register   */
/*****************************************************/
#define UHC_BASE        0x7BC00000              /* base address of USB2.0FS Host/USB2.0LS Host Control Register */
#define USBConfig       (UHC_BASE+0x00)         /* USB configuration register */
#define DMACtl          (UHC_BASE+0x04)         /* DMA control register */
#define RstPDownCtl     (UHC_BASE+0x08)         /* Reset power down control register */
#define HostCtl         (UHC_BASE+0x20)         /* Host Control register */
#define SttTrnsCnt      (UHC_BASE+0x24)         /* Status, RD/WR FIFO transfer length register */
#define PktDataTrnsReq  (UHC_BASE+0x28)         /* Packet data transfer request register */
#define RamAdr          (UHC_BASE+0x30)         /* Internal RAM address setting register */
#define FifoAcc         (UHC_BASE+0x40)         /* FIFO access register */
#define USBPortMon      (UHC_BASE+0xA0)         /* USB Port monitor register */
#define USBPortCtl      (UHC_BASE+0xB0)         /* USB Port control register */
#define HcRevision      (UHC_BASE+0x100)        /* HcRevision register */
#define HcControl       (UHC_BASE+0x104)        /* HcControl register */
#define HcCommandStatus (UHC_BASE+0x108)        /* HcCommandStatus register */
#define HcInterruptStatus (UHC_BASE+0x10C)        /* HcInterruptStatus register */
#define HcInterruptEnable (UHC_BASE+0x110)        /* HcInterruptEnable register */
#define HcInterruptDisable (UHC_BASE+0x114)        /* HcInterruptDisable register */
#define HcHCCA          (UHC_BASE+0x118)        /* HcHCCA register */
#define HcPeriodCurrentED (UHC_BASE+0x11C)        /* HcPeriodCurrentED register */
#define HcControlHeadED (UHC_BASE+0x120)        /* HcControlHeadED register */
#define HcControlCurrentED (UHC_BASE+0x124)        /* HcControlCurrentED register */
#define HcBulkHeadED    (UHC_BASE+0x128)        /* HcBulkHeadED register */
#define HcBulkCurrentED (UHC_BASE+0x12C)        /* HcBulkCurrentED register */
#define HcDoneHead      (UHC_BASE+0x130)        /* HcDoneHead register */
#define HcFmInterval    (UHC_BASE+0x134)        /* HcFmInterval register */
#define HcFmRemaining   (UHC_BASE+0x138)        /* HcFmRemaining register */
#define HcFmNumber      (UHC_BASE+0x13C)        /* HcFmNumber register */
#define HcPeriodicStart (UHC_BASE+0x140)        /* HcPeriodicStart register */
#define HcLSThreshold   (UHC_BASE+0x144)        /* HcLSThreshold register */
#define HcRhDescriptorA (UHC_BASE+0x148)        /* HcRhDescriptorA register */
#define HcRhDescriptorB (UHC_BASE+0x14C)        /* HcRhDescriptorB register */
#define HcRhStatus      (UHC_BASE+0x150)        /* HcRhStatus register */
#define HcRhPortStatus  (UHC_BASE+0x154)        /* HcRhPortStatus register */

/* bit field of USBConfig register */
#define USBConfig_FFBUFSELN0    0x00000001      /* Reserved */
#define USBConfig_EXBUFENB0     0x00000004      /* Disable on-chip USB receiver */
#define USBConfig_TRMODE        0x00000030      /* Reserved */

/* bit field of DMACtl register */
#define DMACtl_DREQltvl         0x00000F00      /* DREQ output interval */

/* bit field of RstPDownCtl register */
#define RstPDownCtl_SOFTRST     0x00000001      /* Reset USB Host block */
#define RstPDownCtl_CLKSTOP     0x00000002      /* Clock disable and power down */
#define RstPDownCtl_BUSY        0x00000004      /* Indicate SW/HW reset was accepted */

/* bit field of HostCtl register */
#define HostCtl_DMAIRQMASK      0x00000001      /* Mask for packet data transfer interrupt */
#define HostCtl_OHCIIRQMASK     0x00000002      /* Mask for OHCI control interrupt */

/* bit field of SttTrnsCnt register */
#define SttTrnsCnt_DMAIRQ       0x00000001      /* Interrupt request for packet data transfer */
#define SttTrnsCnt_OHCIIRQ      0x00000002      /* Interrupt request from OHCI register/host core */

/* bit field of PktDataTrnsReq register */
#define PktDataTrnsReq_DMADIR   0x00000001      /* Packet transfer direction when packet transfer interrupt occurred */
#define PktDataTrnsReq_DMASTART 0xFFFFFFFC      /* Packet transfer start address when packet transfer interrupt occurred */

/* bit field of RamAdr register */
#define RamAdr_IRAMBASE13_12    0x00003000      /* Reserved */
#define RamAdr_IRAMBASE         0xFFFFC000      /* Start address related to internal RAM */

/* bit field of USBPortMon register */
#define USBPortMon_PORT0ENB     0x00000001      /* Enable D+/D- observation */
#define USBPortMon_PORT0IN      0x00000006      /* PORT0IN = {VP[0], VM[0]} */

/* bit field of USBPortCtl register */
#define USBPortCtl_GN_SE_ENB    0x00000001      /* Compulsive set the input-enable-port in on-chip internal USB receiver  */
#define USBPortCtl_GN_SE_VAL    0x00000002      /* The data bit for compulsive setting input-enable-port in on-chip internal USB receiver  */
#define USBPortCtl_PCONTN_ENB   0x00000010      /* Compulsive output PCONTN_VAL through USB0PENC port */
#define USBPortCtl_PCONTN_VAL   0x00000020      /* The data bit for compulsive setting for USB0PENC output port */

/* bit field of HcControl register */
#define HcControl_CBSR          0x00000003      /* Control Bulk Service Ratio */
#define HcControl_PLE           0x00000004      /* Periodic List Enable */
#define HcControl_IE            0x00000008      /* Isochronous Enable */
#define HcControl_CLE           0x00000010      /* Control List Enable */
#define HcControl_BLE           0x00000020      /* Bulk List Enable */
#define HcControl_HCFS          0x000000C0      /* Host Controller Functional State */
#define HcControl_IR            0x00000100      /* Interrupt Routing */
#define HcControl_WC            0x00000200      /* Remote Wakeup Connected */
#define HcControl_RWE           0x00000400      /* Remote Wakeup Enable */

/* bit field of HcCommandStatus register */
#define HcCommandStatus_HCR     0x00000001      /* Host Controller Reset */
#define HcCommandStatus_CLF     0x00000002      /* Control List Filled */
#define HcCommandStatus_BLF     0x00000004      /* Bulk List Filled */
#define HcCommandStatus_OCR     0x00000008      /* Ownership Change Request */
#define HcCommandStatus_SOC     0x00030000      /* Scheduling Overrun Count */

/* bit field of HcInterruptStatus register */
#define HcInterruptStatus_SO    0x00000001      /* Scheduling Overrun */
#define HcInterruptStatus_WDH   0x00000002      /* Writeback Done Head */
#define HcInterruptStatus_SF    0x00000004      /* Start of Frame */
#define HcInterruptStatus_RD    0x00000008      /* Resume Detected */
#define HcInterruptStatus_UE    0x00000010      /* Unrecoverable Error */
#define HcInterruptStatus_FNO   0x00000020      /* Frame Number Overflow */
#define HcInterruptStatus_RHSC  0x00000040      /* Root Hub Status Change */
#define HcInterruptStatus_OC    0x40000000      /* Ownership Change */

/* bit field of HcInterruptEnable register */
#define HcInterruptEnable_SO    0x00000001      /* Scheduling Overrun */
#define HcInterruptEnable_WDH   0x00000002      /* Writeback Done Head */
#define HcInterruptEnable_SF    0x00000004      /* Start of Frame */
#define HcInterruptEnable_RD    0x00000008      /* Resume Detected */
#define HcInterruptEnable_UE    0x00000010      /* Unrecoverable Error */
#define HcInterruptEnable_FNO   0x00000020      /* Frame Number Overflow */
#define HcInterruptEnable_RHSC  0x00000040      /* Root Hub Status Change */
#define HcInterruptEnable_OC    0x40000000      /* Ownership Change */
#define HcInterruptEnable_MIE   0x80000000      /* Master Interrupt Enable */

/* bit field of HcInterruptDisable register */
#define HcInterruptDisable_SO   0x00000001      /* Scheduling Overrun */
#define HcInterruptDisable_WDH  0x00000002      /* Writeback Done Head */
#define HcInterruptDisable_SF   0x00000004      /* Start of Frame */
#define HcInterruptDisable_RD   0x00000008      /* Resume Detected */
#define HcInterruptDisable_UE   0x00000010      /* Unrecoverable Error */
#define HcInterruptDisable_FNO  0x00000020      /* Frame Number Overflow */
#define HcInterruptDisable_RHSC 0x00000040      /* Root Hub Status Change */
#define HcInterruptDisable_OC   0x40000000      /* Ownership Change */
#define HcInterruptDisable_MIE  0x80000000      /* Master Interrupt Enable */

/* bit field of HcHCCA register */
#define HcHCCA_HCCA             0xFFFFFF00      /* Host Controller Communications Area */

/* bit field of HcPeriodCurrentED register */
#define HcPeriodCurrentED_PCED  0xFFFFFFF0      /* Period Current ED */

/* bit field of HcControlHeadED register */
#define HcControlHeadED_CHED    0xFFFFFFF0      /* Control Head ED */

/* bit field of HcControlCurrentED register */
#define HcControlCurrentED_CCED 0xFFFFFFF0      /* Control Current ED */

/* bit field of HcBulkHeadED register */
#define HcBulkHeadED_BHED       0xFFFFFFF0      /* Bulk Head ED */

/* bit field of HcBulkCurrentED register */
#define HcBulkCurrentED_BCED    0xFFFFFFF0      /* Bulk Current ED */

/* bit field of HcDoneHead register */
#define HcDoneHead_DH           0xFFFFFFF0      /* Done Head ED */

/* bit field of HcFmInterval register */
#define HcFmInterval_FI         0x00003FFF      /* Frame Interval */
#define HcFmInterval_FSMPS      0x7FFF0000      /* FS Largest Data Packet */
#define HcFmInterval_FIT        0x80000000      /* Frame Interval Toggle */

/* bit field of HcFmRemaining register */
#define HcFmRemaining_FR        0x00003FFF      /* Frame Remaining */
#define HcFmRemaining_FRT       0x80000000      /* Frame Remaining Toggle */

/* bit field of HcFmNumber register */
#define HcFmNumber_FN           0x0000FFFF      /* Frame Number */

/* bit field of HcPeriodicStart register */
#define HcPeriodicStart_PS      0x00003FFF      /* Periodic Start */

/* bit field of HcLSThreshold register */
#define HcLSThreshold_LT        0x00000FFF      /* LS Threshold */

/* bit field of HcRhDescriptorA register */
#define HcRhDescriptorA_NDP     0x000000FF      /* Number Downstream Ports */
#define HcRhDescriptorA_PSM     0x00000100      /* Power Switching Mode */
#define HcRhDescriptorA_NPS     0x00000200      /* No Power Switching */
#define HcRhDescriptorA_DT      0x00000400      /* Device Type */
#define HcRhDescriptorA_OCPM    0x00000800      /* Overcurrent Protection Mode */
#define HcRhDescriptorA_NOCP    0x00001000      /* No Overcurrent Protection */
#define HcRhDescriptorA_POTPGT  0xFF000000      /* Power On to Power Good Time */

/* bit field of HcRhDescriptorB register */
#define HcRhDescriptorB_DR      0x00000002      /* Device Removable */
#define HcRhDescriptorB_PPCM    0x00020000      /* Port Power Control Mask */

/* bit field of HcRhStatus register */
#define HcRhStatus_LPS          0x00000001      /* Local Power Status */
#define HcRhStatus_OCI          0x00000002      /* Overcurrent Indicator */
#define HcRhStatus_DRWE         0x00008000      /* Device Remote Wakeup Enable */
#define HcRhStatus_LPSC         0x00010000      /* Local Power Status Change */
#define HcRhStatus_OCIC         0x00020000      /* Overcurrent Indicator Change */
#define HcRhStatus_CRWE         0x80000000      /* Clear Remote Wakeup Enable */

/* bit field of HcRhPortStatus register */
#define HcRhPortStatus_CCS      0x00000001      /* Current Connect Status */
#define HcRhPortStatus_PES      0x00000002      /* Port Enable Status */
#define HcRhPortStatus_PSS      0x00000004      /* Port Suspend Status */
#define HcRhPortStatus_POCI     0x00000008      /* Port Overcurrent Indicator */
#define HcRhPortStatus_PRS      0x00000010      /* Port Reset Status */
#define HcRhPortStatus_PPS      0x00000100      /* Port Power Status */
#define HcRhPortStatus_LSDA     0x00000200      /* Low-speed Device Attached */
#define HcRhPortStatus_CSC      0x00010000      /* Connect Status Change */
#define HcRhPortStatus_PESC     0x00020000      /* Port Enable Status Change */
#define HcRhPortStatus_PSSC     0x00040000      /* Port Suspend Status Change */
#define HcRhPortStatus_OCIC     0x00080000      /* Port Overcurrent Indicator Change */
#define HcRhPortStatus_PRSC     0x00100000      /* Port Reset Status Change */


/*****************************************************/
/*    DMA Control Register                           */
/*****************************************************/
#define DMA_BASE        0x7BE00000              /* base address of DMA Control Register */
#define DMAMODA         (DMA_BASE+0x00)         /* DMA mode register A */
#define DMASTAA         (DMA_BASE+0x04)         /* DMA status register A */
#define DMAINTA         (DMA_BASE+0x08)         /* DMA termination status register A */
#define DMACMSKA0       (DMA_BASE+0x100)        /* DMA channel mask register A0 */
#define DMACTMODA0      (DMA_BASE+0x104)        /* DMA transger mode register A0 */
#define DMACSADA0       (DMA_BASE+0x108)        /* DMA transfer source address register A0 */
#define DMACDADA0       (DMA_BASE+0x10C)        /* DMA transfer destination address register A0 */
#define DMACSIZA0       (DMA_BASE+0x110)        /* DMA transfer count register A0 */