hal_xbus.c

最新版IAR FOR ARM（EWARM）5.11中的代码例子

/************************************************************************/
/*                                                                      */
/*    Copyright (C) 2006 Oki Electric Industry Co., LTD.                */
/*                                                                      */
/*    System Name    :  uPLAT7D series                                  */
/*    Module Name    :  uPLAT7D xbus HAL program                        */
/*    File   Name    :  hal_xbus.c                                      */
/*    Date           :  2005/12/27 initial version                      */
/*                                                                      */
/************************************************************************/

#include "common.h"
#if defined(__arm)
#include "ml675050.h"
#else
#include "ml675050sim.h"
#endif
#include "hal_common.h"
#include "hal_xbus.h"


/************************************************************************/
/*                                                                      */
/*  Function Name   : HAL_Xbus_InitMem                                  */
/*  Input           : param Parameter of xbus.                          */
/*  Output          : void                                              */
/*                                                                      */
/*  Note : Initialize xbus.                                             */
/*                                                                      */
/************************************************************************/
void HAL_Xbus_InitMem(uPLAT_XbusParam *param) {
    uint16_t i;

    if (param->standby == FALSE) {
        /* bus width control register. */
        OkiCLib_write32(BWC, param->rombw     /* ROM bus width */
                             | param->srambw  /* SRAM bus width */
                             | param->iobw);  /* IO bus width */

        /* ROM access control register. */
        OkiCLib_write32(ROMAC, param->romtype      /* ROM type */
                               | param->rombrst);  /* ROM page mode */

        /* SRAM access control register. */
        OkiCLib_write32(RAMAC, param->sramtype     /* SRAM type */
                               | param->srambrst); /* SRAM page mode */

        /* IO access control register. */
        OkiCLib_write32(IOAC, param->iotype);      /* IO type */
    }

    /* wait >=200us */
    for(i = 0; i < 0x96E; i++) {
        ;
    }

#if USB_USED

    /* SDRAM bus width control register. */
    OkiCLib_write32(DBWC, param->sdrambw);

    /* DRAM control register. */
    OkiCLib_write32(DRMC, DRMC_9bit         /* AMUX:9bit */
                          | DRMC_SDRAM      /* ARCH:SDRAM */
                          | DRMC_2CLK       /* prelat: 2clock */
                          | DRMC_PD_DIS     /* PDWN: disable */
                          | DRMC_CBR_STOP); /* CBR: stop */

    /* DRAM parameter control register. */
    OkiCLib_write32(DRPC, DRPC_DRAMSPEC_2);

    /* DRAM refresh cycle control register. */
    OkiCLib_write32(RFSH, RFSH_RCCON_0);
    OkiCLib_write32(RFGC, RFGC_RFSEL_2000);

    /* DRAM power down mode control register. */
    OkiCLib_write32(PDWC, PDWC_9);

    /* All bank pre-charge. */
    OkiCLib_write32(DCMD, DCMD_S_PALL);

    /* CBR reflash 8 timers. */
    for (i = 0; i < 8; i++) {
        OkiCLib_write32(DCMD, DCMD_S_REF);
    }

    /* SDRAM mode register. */
    OkiCLib_write32(SDMD, SDMD_CL2        /* 2clock */
                          | SDMD_MODEWR); /* setting operation : valid */

    /* PDWN: enable */
    OkiCLib_set32bit(DRMC, DRMC_PD_EN);
        
    if (param->standby == FALSE) {
        /* CBR: execute */
        OkiCLib_set32bit(DRMC, DRMC_CBR_EXE); 
    }

#else

    /* SDRAM bus width control register. */
    OkiCLib_write32(DBWC, param->sdrambw);

    /* DRAM control register. */
    OkiCLib_write32(DRMC, DRMC_9bit         /* AMUX:9bit */
                          | DRMC_SDRAM      /* ARCH:SDRAM */
                          | DRMC_2CLK       /* prelat: 2clock */
                          | DRMC_PD_DIS     /* PDWN: disable */
                          | DRMC_CBR_STOP); /* CBR: stop */

    /* DRAM parameter control register. */
    OkiCLib_write32(DRPC, DRPC_DRAMSPEC_0);

    /* DRAM refresh cycle control register. */
    OkiCLib_write32(RFSH, RFSH_RCCON_0);
    OkiCLib_write32(RFGC, RFGC_RFSEL_250);

    /* DRAM power down mode control register. */
    OkiCLib_write32(PDWC, PDWC_9);

    /* All bank pre-charge. */
    OkiCLib_write32(DCMD, DCMD_S_PALL);

    /* CBR reflash 8 timers. */
    for (i = 0; i < 8; i++) {
        OkiCLib_write32(DCMD, DCMD_S_REF);
    }

    /* SDRAM mode register. */
    OkiCLib_write32(SDMD, SDMD_CL2        /* 2clock */
                          | SDMD_MODEWR); /* setting operation : valid */

    /* PDWN: enable */
    OkiCLib_set32bit(DRMC, DRMC_PD_EN);

    if (param->standby == FALSE) {
        /* CBR: execute */
        OkiCLib_set32bit(DRMC, DRMC_CBR_EXE);
    }

#endif

}