irq.s
来自「最新版IAR FOR ARM(EWARM)5.11中的代码例子」· S 代码 · 共 71 行
S
71 行
//*********************************************************************
// irq.s
//
// Interrupt entry/exit code for IRQ
//
//
// Copyright (c) 2000 Micronas GmbH, Author: P. Bonello
//
// History: 04.04.05 created
//*********************************************************************
EXPORT IRQHandler
IMPORT IRQ_Counter
IMPORT VECTAB_1
IMPORT isr_def
SECTION CSTACK:DATA:NOROOT(3)
IRQ_COUNTER_ADDR
DCD IRQ_Counter
SECTION CODE:CODE:NOROOT(2)
ARM // Always ARM mode after reset
IRQHandler
SUB lr, lr, #4 //adjust the return address
STMFD sp!, {lr} //stack return address
MRS r14, SPSR //push LR_irq, SPSR_irq and a work register onto the stack
//to stop them being corrupted when another interrupt occurs
STMFD sp!, {r12,r14}
#ifdef __DEBUG
//increment global IRQ counter
STMFD sp!, {r1}
LDR r12, IRQ_COUNTER_ADDR
LDR r1, [r12] //read address of ISR and clear interrupt in controller (-->IAck)
ADD r1, r1, #1
STR r1, [r12]
LDMFD sp!, {r1}
#endif
LDR r12, VECTAB_1
MSR CPSR_c, #0x1F //switch to system mode, IRQ enabled, FIQ enabled (###0.12)
STMFD sp!, {r0-r3,lr} //save registers and LR_user on user mode stack,
MOV LR, PC //prepare LR for ISR return
BX r12 //*** branch to ISR (can be Thumb or ARM code, depending of bit 0 in vector table entry)
LDMFD sp!, {r0-r3,lr} //restore the pushed registers
MSR CPSR_c, #0x12+0x80 //switch to IRQ mode, IRQ disabled, FIQ enabled (###0.12)
//(###0.12
LDR r14, =isr_def //compare the vector with the default vector
CMP r12, r14
BEQ IEXIT_READY //in case of def. vector IExit should not be generated hereafter
//###0.12)
LDR r12, =VECTAB_1
STR r0, [r12,#0x100] //write access to IExit
IEXIT_READY //###0.12
LDMFD sp!, {r12,r14} //restore work register, LR and SPSR
MSR SPSR_cxsf, r14 //and return from exception using
LDMFD sp!, {PC}^ //modified LR
LTORG
END
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