startup.s

来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· S 代码 · 共 238 行

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Part one of the system initialization code,
;; contains low-level
;; initialization.
;;
;; Copyright 2006 IAR Systems. All rights reserved.
;;
;; $Revision: 15571 $
;;

;---------------------------------------------------------------
; Macros and definitions for the whole file
;---------------------------------------------------------------

; Mode, correspords to bits 0-5 in CPSR
MODE_BITS DEFINE  0x1F    ; Bit mask for mode bits in CPSR
USR_MODE  DEFINE  0x10    ; User mode
FIQ_MODE  DEFINE  0x11    ; Fast Interrupt Request mode
IRQ_MODE  DEFINE  0x12    ; Interrupt Request mode
SVC_MODE  DEFINE  0x13    ; Supervisor mode
ABT_MODE  DEFINE  0x17    ; Abort mode
UND_MODE  DEFINE  0x1B    ; Undefined Instruction mode
SYS_MODE  DEFINE  0x1F    ; System mode

WORD_CONST_CTRL_WRD             DEFINE  0xFFFFFF5F  ; Processor Control Word: MAP = 01, JTAG = 0, EBW = 1
                                                    ;  (-> ignore most significant half word)
                                                    ;
WORD_CONST_EMPTY_SECUVECD       DEFINE  0xFFFFFFFF  ; 'empty'-value for security vector, has to be treated separately
HALF_WORD_CONST_ROM_ID          DEFINE  0xFFFF      ; ROM identification value = ROM No., tbd (insert correct one)
HALF_WORD_CONST_ROM_RESVD       DEFINE  0xFFFF      ; Boot ROM value for reserved location (adr. 0x0000002A)
WORD_CONST_FACTORY_ID           DEFINE  0x00000000  ; Boot ROM factory identification value for reserved location
                                                    ;
; CEVG register addresses:
BYTE_ADDR_CONST_HW_OPTIONS_REGS DEFINE 0x00F901C0  ; start addr. of CEVG HW options registers
HW_OPTIONS                      DEFINE 0x00000030  ; start addr. of CEVG HW options in Flash
REG_H0D                         DEFINE 0x00F904C0

;---------------------------------------------------------------
; ?RESET
; Reset Vector.
; Normally, segment INTVEC is linked at address 0.
; For debugging purposes, INTVEC may be placed at other
; addresses.
; For the exception vectors (0x00 - 0x1C), insert the correct
; labels if exception handler functions are available.
;---------------------------------------------------------------

        MODULE  ?cstartup

        SECTION .intvec:CODE:NOROOT(2)

        PUBLIC  __vector
        PUBLIC  __iar_program_start
        EXTERN  IRQHandler, FIQHandler

__program_start
        ARM ; Always ARM mode after reset

; If WinFlash + the bootloader stored in the last sector are used to download an application in Flash,
; the reset location will redirect the program straight to the last sector (bootloader entry point).
; The preprocessor macro 'WIN_FLASH_BL' must be defined. Then the flash tipe 'FLASH_AMD' or
; 'FLASH_SST' must be defined.
; Otherwise a branch to'cstartup' is performed.
__vector
#ifdef WIN_FLASH_BL
#ifdef FLASH_AMD
                  MOV PC, #0x7C000  ; RESET (branch to boot loader
                                    ; @ 0x3c000 in AMD LV200
                                    ; @ 0x7c000 in AMD LV400
                                    ; @ 0xfc000 in AMD LV800
#endif
#ifdef FLASH_SST
                  MOV PC, #0x70000  ; RESET (branch to boot loader
                                    ; @ 0x30000 in SST VF200)
                                    ; @ 0x70000 in SST VF400)
                                    ; @ 0xF0000 in SST VF800)
#endif
undef_handler     B   ?cstartup     ; 0x04 - Undefined instruction

#else
                  B   ?cstartup     ; 0x00 - RESET
undef_handler     B   undef_handler ; 0x04 - Undefined instruction
#endif
swi_handler       B   swi_handler   ; 0x08 - Software interrupt
prefetch_handler  B   prefetch_handler  ; 0x0c - Prefetch abort (instruction fetch memory abort)
data_handler      B   data_handler  ; 0x10 - Data Abort (data access memory abort)
                  DC32 0xFFFFFFFF   ; 0x14 - Reserved -
                  B   IRQHandler    ; 0x18 - Interrupt
                  B   FIQHandler    ; 0x1c - Fast Interrupt

; Constant table entries (for ldr pc) will be placed at 0x20
; CEVG specific data:
control_word      ; ORG 0x00000020 - 0x00000023, 4 bytes
                  dc32  WORD_CONST_CTRL_WRD
;
security_vector   ; ORG 0x00000024 - 0x00000027, 4 bytes
                  dc32  WORD_CONST_EMPTY_SECUVECD
;
rom_id            ; ORG 0x00000028 - 0x00000029, 2 bytes
                  dc16  HALF_WORD_CONST_ROM_ID
;
reserved          ; ORG 0x0000002A - 0x0000002B, 2 bytes
                  dc16  HALF_WORD_CONST_ROM_RESVD
;
factory_id        ; ORG 0x0000002C - 0x0000002F, 4 bytes
                  dc32  WORD_CONST_FACTORY_ID
;
;CEVG Hardware Options data:
hw_options        ; ORG 0x00000030 - 0x0000005F, 48 bytes
                  dc8 0x09 ;0x00 T0C Timer 0 Clock
                  dc8 0x06 ;0x01 T1C Timer 1 Clock
                  dc8 0x06 ;0x02 T2C Timer 2 Clock
                  dc8 0x06 ;0x03 T3C Timer 3 Clock
                  dc8 0x06 ;0x04 T4C Timer 4 Clock
                  dc8 0x11 ;0x05 CO00C Clock Out 0: Mux0 Pre. & Clock
                  dc8 0x00 ;0x06 CO01C Clock Out 0: Mux1 Clock
                  dc8 0x09 ;0x07 CO02C Clock Out 0: Mux2 Clock
                  dc8 0x00 ;0x08 DMAC DMA Timer Clock
                  dc8 0x11 ;0x09 CO1C Clock Out 1: Pre. & Clock
                  dc8 0x04 ;0x0A C0C CAPCOM Counter 0 Clock
                  dc8 0x06 ;0x0B C1C CAPCOM Counter 1 Clock
                  dc8 0x00 ;0x0C DC DIGITbus Clock
                  dc8 0x03 ;0x0D LC LCD Pre. & Clock
                  dc8 0x01 ;0x0E AC AM Clock
                  dc8 0x00 ;0x0F PF0C PFM 0 Clock
                  dc8 0x01 ;0x10 SMC SM, SPI0, SPI1 Pre. & SM Clock
                  dc8 0x00 ;0x11 SP0C SPI0 I/O & F0 SPI Clock
                  dc8 0x00 ;0x12 SP1C SPI1 I/O & F1 SPI Clock
                  dc8 0x00 ;0x13 SP2C F2 SPI Clock
                  dc8 0x00 ;0x14 P9C PWM 8, 9 Clock
                  dc8 0x08 ;0x15 P9P PWM 8, 9 Period
                  dc8 0x00 ;0x16 P11C PWM 10, 11 Clock
                  dc8 0x08 ;0x17 P11P PWM 10, 11 Period
                  dc8 0x08 ;0x18 P1C PWM 0, 1 Clock
                  dc8 0x10 ;0x19 P1P PWM 0, 1 Period
                  dc8 0x08 ;0x1A P3C PWM 2, 3 Clock
                  dc8 0x10 ;0x1B P3P PWM 2, 3 Period
                  dc8 0x00 ;0x1C P5C PWM 4, 5 Clock
                  dc8 0x08 ;0x1D P5P PWM 4, 5 Period
                  dc8 0x00 ;0x1E P7C PWM 6, 7 Clock
                  dc8 0x08 ;0x1F P7P PWM 6, 7 Period
                  dc8 0xFF ;0x20
                  dc8 0xFF ;0x21
                  dc8 0xFF ;0x22
                  dc8 0xFF ;0x23
                  dc8 0xFF ;0x24
                  dc8 0xFF ;0x25
                  dc8 0xFF ;0x26
                  dc8 0xFF ;0x27
                  dc8 0xFF ;0x28
                  dc8 0x30 ;0x29 PM Port Mux
                  dc8 0x00 ;0x2A CM Clock Monitor
                  dc8 0xFF ;0x2B
                  dc8 0x00 ;0x2C UA0 UART0 I/O
                  dc8 0x00 ;0x2D UA1 UART1 I/O
                  dc8 0xFF ;0x2E
                  dc8 0xFF ;0x2F


; --------------------------------------------------
; ?cstartup -- low-level system initialization code.
;
; After a reser execution starts here, the mode is ARM, supervisor
; with interrupts disabled.
;


        ;; Forward declaration of sections.
        SECTION IRQ_STACK:DATA:NOROOT(4)
        SECTION FIQ_STACK:DATA:NOROOT(4)
        SECTION SVC_STACK:DATA:NOROOT(4)
        SECTION ABT_STACK:DATA:NOROOT(4)
        SECTION UND_STACK:DATA:NOROOT(4)
        SECTION CSTACK:DATA:NOROOT(4)

        SECTION .text:CODE:NOROOT(2)

;        PUBLIC  ?cstartup
        EXTERN  ?main
        REQUIRE __vector

        ARM

__iar_program_start:
?cstartup:

; Add initialization nedded before setup of stackpointers here

; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS.
; The stack segments must be defined in the linker command file,
; and be declared above.

                MOV     R4,SP                 ; save SP
                LDR     SP,=SFE(SVC_STACK)    ; setup Supervisor Mode stack pointer

                MSR     CPSR_c,#128+64+16+7   ; DI IRQ FIQ change to ABORT mode
                LDR     SP,=SFE(ABT_STACK)    ; setup ABORT Mode stack pointer

                MSR     CPSR_c,#128+64+16+11  ; DI IRQ FIQ change to UNDEF mode
                LDR     SP,=SFE(UND_STACK)    ; setup UNDEF mode stack pointer

                MSR     CPSR_c,#128+64+16+2   ; DI IRQ FIQ change to IRQ mode
                LDR     SP,=SFE(IRQ_STACK)    ; setup IRQ mode stack pointer

                MSR     CPSR_c,#128+64+16+1   ; DI IRQ FIQ change to FIQ mode
                LDR     SP,=SFE(FIQ_STACK)    ; setup FIQ mode stack pointer

                MSR     CPSR_c,#16+0          ; EI IRQ FIQ change to USER mode
                LDR     SP,=SFE(CSTACK)       ; setup USER mode stack pointer

; set CEVG Hardware Options:
                LDR     r1,=BYTE_ADDR_CONST_HW_OPTIONS_REGS ; load first target address
                MOV     r3, #48               ; program 48 bytes
                LDR     r0,=HW_OPTIONS        ; load first source address
copy_hw_option
                ldr     r2,[r0],#4            ; read option value / next source address
                str     r2,[r1],#4            ; write option value / next target address
                SUBS    R3,R3,#4              ; all done?
                BNE     copy_hw_option        ; branch if not

; Add more initialization here


; Continue to ?main for more IAR specific system startup

                ldr     r0,=?main
                bx      r0

                END