drv_csi.c

来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· C语言 代码 · 共 95 行

/*************************************************************************
 *
 *    Used with ICCARM and AARM.
 *
 *    (c) Copyright IAR Systems 2007
 *
 *    File name   : drv_csi.c
 *    Description : CSI driver module
 *
 *    History :
 *    1. Date        : May, 3 2007
 *       Author      : Stanimir Bonev
 *       Description : Create
 *
 *    $Revision: 1.2 $
 **************************************************************************/
#include "drv_csi.h"
extern Int8U LcdBuff[LCD_WIDTH*LCD_HEIGHT*(LCD_BPP/8)];

static Boolean Csi_Enable;

/*************************************************************************
 * Function Name: Csi_Handler
 * Parameters: none
 *
 * Return: none
 *
 * Description: CSI interrupt handler
 *
 *************************************************************************/
void Csi_Handler (void)
{
  PRP_INTRSTATUS_bit.CH1B1CI = 1;
  PRP_CNTL_bit.CH1EN = Csi_Enable;
}

/*************************************************************************
 * Function Name: Csi_init
 * Parameters: none
 *
 * Return: none
 *
 * Description: Init CSI module
 *
 *************************************************************************/
void Csi_init (void)
{
Int8U Csi_Data[2];

  // Camera reset
  CSI_RST_L();
  CSI_STB_L();
  CSI_RST_H();

  // Set PERDIV4 ~ 53MHz
  PCDR1_bit.PCLK_DIV4 = 5 - 1;
  PCCR0_bit.PERCLK4_EN = 1;
  PCCR0_bit.HCLK_CSI_EN = 1;

  //module init
  // The pins assign to the CSI module
  // CSI_D0-D7, CSI_HSYNC, CSI_VSYNC, CSI_PIXCLK, CSI_MCLK
  PTB_GIUS &= ~(0xFFF<<10);       // disable GPIO PB[21..10]
  CSICR1 = 0x0;                   // register clear
  CSICR1_bit.MCLKDIV = 1;         // MCLK = 13.5MHz HCLK/4
  //timing control
  CSICR1_bit.SOF_POL = 1;         // SOF rising edge
  CSICR1_bit.SOF_INTEN = 1;       // SOF INT enable
  CSICR1_bit.REDGE = 1;           // latch on rising edge
  CSICR1_bit.GCLK_MODE = 1;       // gated clock mode
  CSICR1_bit.HSYNC_POL = 1;       // hsync active high
  //FIFO control
  CSICR1_bit.FCC = 1;             // sync FIFO clear
  CSICR1_bit.RXFF_LEVEL = 2;      // RXFF level = 16
  //data manipulation
  CSICR1_bit.SWAP16_EN = 0;       // swap16 disable
  CSICR1_bit.PACK_DIR = 0;        // little endian
  //PRP i/f control
  CSICR1_bit.PRP_IF_EN = 1;       // PRP i/f enable
  CSICR1_bit.MCLKEN = 1;          // MCLK enable

  // Init PrP
  PCCR0_bit.EMMA_EN = 1;          // Clock enable for PRP
  PCCR0_bit.HCLK_EMMA_EN = 1;     // Enable EMMA AHB clock input
  PRP_CNTL_bit.SWRST = 1;         // PRP reset
  //YUV 4:2:2 => CamOutBuff565 (ch1)
  //common control
  PRP_CNTL_bit.CSIEN = 1;         // CSI connection enable
  PRP_CNTL_bit.DATA_IN_MODE = 1;  // 1 = YUV 4:2:2;2 = CSI 16-bit CamOutBuff data
  PRP_CNTL_bit.CH1_OUT_MODE = 1;  // Output format 16 bpp CamOutBuff
  PRP_CNTL_bit.CH1_LEN = 1;       // CH1 Loop mode
  PRP_CNTL_bit.CH1BYP = 1;        // Disable cascade of Channel-1 resize
  PRP_CNTL_bit.IN_TSKIP = 0;      // no skip input frames
  PRP_CNTL_bit.CH1_TSKIP = 0;     // no skip output frames
  PRP_CNTL_bit.INPUT_FIFO_LEVEL = 0; // Input FIFO Level