lowlevel.c

来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· C语言 代码 · 共 259 行

/* ----------------------------------------------------------------------------
 *         ATMEL Microcontroller Software Support  -  ROUSSET  -
 * ----------------------------------------------------------------------------
 * Copyright (c) 2006, Atmel Corporation
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * - Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the disclaiimer below.
 *
 * - Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the disclaimer below in the documentation and/or
 * other materials provided with the distribution.
 *
 * Atmel's name may not be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * ----------------------------------------------------------------------------
 */
/*-----------------------------------------------------------------------------
 *  File Name           : lowlevel.c
 *  Object              : low level initialization file
 *  Creation            : FDy   20-Nov-2006
 *-----------------------------------------------------------------------------
 */

/* Include Standard files */
#include "project.h"


/*-----------------------------------------------------------------------------
 * Function Name       : default_spurious_handler
 * Object              : default handler for spurious interrupt
 *-----------------------------------------------------------------------------*/
void default_spurious_handler(void)
{
    dbgu_print_ascii("-F- Spurious Interrupt\n\r ");
    while (1);
}

/*-----------------------------------------------------------------------------
 * Function Name       : default_fiq_handler
 * Object              : default handler for fast interrupt
 *-----------------------------------------------------------------------------*/
void default_fiq_handler(void)
{
    dbgu_print_ascii("-F- Unexpected FIQ Interrupt\n\r ");
    while (1);
}

/*-----------------------------------------------------------------------------
 * Function Name       : default_irq_handler
 * Object              : default handler for irq
 *-----------------------------------------------------------------------------*/
void default_irq_handler(void)
{
    dbgu_print_ascii("-F- Unexpected IRQ Interrupt\n\r ");
    while (1);
}

//*--------------------------------------------------------------------------------------
//* Function Name       : AT91F_InitSdram
//* Object              : Initialize the SDRAM
//*--------------------------------------------------------------------------------------
void init_SDRAMC (void)
{
    unsigned int i;
    unsigned long *pSDRAM = (unsigned long *)AT91C_EBI_SDRAM;

    /* Configure MATRIX for SDRAM on CS1 */
    AT91C_BASE_CCFG->CCFG_EBICSA |= 0x1003A;

    /* Configure PIOs for SDRAM */
    AT91C_BASE_PIOC->PIO_ASR = AT91C_PC20_D20 |
                               AT91C_PC21_D21 |
                               AT91C_PC30_D30 |
                               AT91C_PC22_D22 |
                               AT91C_PC31_D31 |
                               AT91C_PC23_D23 |
                               AT91C_PC16_D16 |
                               AT91C_PC24_D24 |
                               AT91C_PC17_D17 |
                               AT91C_PC25_D25 |
                               AT91C_PC18_D18 |
                               AT91C_PC26_D26 |
                               AT91C_PC19_D19 |
                               AT91C_PC27_D27 |
                               AT91C_PC28_D28 |
                               AT91C_PC29_D29 ;
    AT91C_BASE_PIOC->PIO_BSR = 0;
    AT91C_BASE_PIOC->PIO_PDR = (AT91C_PC20_D20 |
                                AT91C_PC21_D21 |
                                AT91C_PC30_D30 |
                                AT91C_PC22_D22 |
                                AT91C_PC31_D31 |
                                AT91C_PC23_D23 |
                                AT91C_PC16_D16 |
                                AT91C_PC24_D24 |
                                AT91C_PC17_D17 |
                                AT91C_PC25_D25 |
                                AT91C_PC18_D18 |
                                AT91C_PC26_D26 |
                                AT91C_PC19_D19 |
                                AT91C_PC27_D27 |
                                AT91C_PC28_D28 |
                                AT91C_PC29_D29);

    /* Configure SDRAM timings */
    AT91C_BASE_SDRAMC->SDRAMC_CR = AT91C_SDRAMC_NC_9  |
                                   AT91C_SDRAMC_NR_13 |
                                   AT91C_SDRAMC_CAS_2 |
                                   AT91C_SDRAMC_NB_4_BANKS |
                                   AT91C_SDRAMC_DBW_32_BITS |
                                   AT91C_SDRAMC_TWR_2 |
                                   AT91C_SDRAMC_TRC_7 |
                                   AT91C_SDRAMC_TRP_2 |
                                   AT91C_SDRAMC_TRCD_2 |
                                   AT91C_SDRAMC_TRAS_5 |
                                   AT91C_SDRAMC_TXSR_8 ;

    for (i = 0; i < 1000; i++);

    AT91C_BASE_SDRAMC->SDRAMC_MR = 0x00000002; // Set PRCHG AL
    *pSDRAM = 0x00000000;                      // Perform PRCHG

    for (i = 0; i < 10000; i++);

    AT91C_BASE_SDRAMC->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
    *(pSDRAM + 4) = 0x00000001;                                // Perform CBR

    AT91C_BASE_SDRAMC->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 2 CBR
    *(pSDRAM + 8) = 0x00000002;                                // Perform CBR

    AT91C_BASE_SDRAMC->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 3 CBR
    *(pSDRAM + 0xc) = 0x00000003;                              // Perform CBR

    AT91C_BASE_SDRAMC->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 4 CBR
    *(pSDRAM + 0x10) = 0x00000004;                             // Perform CBR

    AT91C_BASE_SDRAMC->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 5 CBR
    *(pSDRAM + 0x14) = 0x00000005;                             // Perform CBR

    AT91C_BASE_SDRAMC->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 6 CBR
    *(pSDRAM + 0x18) = 0x00000006;                             // Perform CBR

    AT91C_BASE_SDRAMC->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 7 CBR
    *(pSDRAM + 0x1c) = 0x00000007;                             // Perform CBR

    AT91C_BASE_SDRAMC->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 8 CBR
    *(pSDRAM + 0x20) = 0x00000008;                             // Perform CBR

    AT91C_BASE_SDRAMC->SDRAMC_MR = AT91C_SDRAMC_MODE_LMR_CMD;  // Set LMR operation
    *(pSDRAM + 0x24) = 0xcafedede;                             // Perform LMR burst=1, lat=2

    // Set Refresh Timer 390 for 25MHz (TR= 15.6 * F ) (F : system clock freq. MHz)
    AT91C_BASE_SDRAMC->SDRAMC_TR = (AT91B_MASTER_CLOCK * 7) / 1000000;

    AT91C_BASE_SDRAMC->SDRAMC_MR = AT91C_SDRAMC_MODE_NORMAL_CMD; // Set Normal mode
    *pSDRAM = 0x00000000;                                        // Perform Normal mode
}

/*-----------------------------------------------------------------------------
 * Function Name       : lowlevel_init
 * Object              : This function performs very low level HW initialization
 *                       this function can use a Stack, depending the compilation
 *                       optimization mode
 *-----------------------------------------------------------------------------*/
void lowlevel_init(void)
{
    unsigned char i = 0;
#ifndef BOOT

    ///////////////////////////////////////////////////////////////////////////
    // Init PMC Step 1. Enable Main Oscillator
    // Main Oscillator startup time is board specific:
    // Main Oscillator Startup Time worst case (3MHz) corresponds to 15ms
    // (0x40 for AT91C_CKGR_OSCOUNT field)
    ///////////////////////////////////////////////////////////////////////////
    AT91C_BASE_PMC->PMC_MOR = (((AT91C_CKGR_OSCOUNT & (0x40 << 8)) | AT91C_CKGR_MOSCEN));
    // Wait Main Oscillator stabilization
    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));

    // Switch to Main Oscillator
    AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_MAIN_CLK;

    ///////////////////////////////////////////////////////////////////////////
    // Init PMC Step 2.
    // Set PLLA to 200MHz (198,656MHz)
    // PLL Startup time depends on PLL RC filter: worst case is choosen
    ///////////////////////////////////////////////////////////////////////////
    AT91C_BASE_PMC->PMC_PLLAR = AT91C_CKGR_SRCA                  |
                                AT91C_CKGR_OUTA_0                |
                                (0xBF << 8)                      |
                                (AT91C_CKGR_MULA & (0x60 << 16)) |
                                (AT91C_CKGR_DIVA & 9);
    // Wait for PLLA stabilization
    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA));
    // Wait until the master clock is established for the case we already
    // turn on the PLLA
    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));

    ///////////////////////////////////////////////////////////////////////////
    // Init PMC Step 3.
    // Selection of Master Clock MCK equal to (Processor Clock PCK) PLLA/2=100MHz
    // The PMC_MCKR register must not be programmed in a single write operation
    // (see. Product Errata Sheet)
    ///////////////////////////////////////////////////////////////////////////
    AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;
    // Wait until the master clock is established
    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));

    AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLLA_CLK;
    // Wait until the master clock is established
    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));

    ///////////////////////////////////////////////////////////////////////////
    // Init SDRAM controller
    ///////////////////////////////////////////////////////////////////////////
    init_SDRAMC();
#endif

    ///////////////////////////////////////////////////////////////////////////
    // Reset AIC: assign default handler for each interrupt source
    ///////////////////////////////////////////////////////////////////////////
    AT91C_BASE_AIC->AIC_SVR[0] = (int) default_fiq_handler ;
    for (i = 1; i < 31; i++) {
        AT91C_BASE_AIC->AIC_SVR[i] = (int) default_irq_handler ;
    }
    AT91C_BASE_AIC->AIC_SPU = (unsigned int) default_spurious_handler;

    // Disable all interrupts
    AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
    // Clear All pending interrupts flags
    AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF;
    // Perform 8 IT acknoledge (write any value in EOICR)
    for (i = 0; i < 8 ; i++) {
        AT91C_BASE_AIC->AIC_EOICR = 0;
    }

    ///////////////////////////////////////////////////////////////////////////
    // Disable Watchdog
    ///////////////////////////////////////////////////////////////////////////
    AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;

}