at91sam9263_lcdc.h

来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· C头文件 代码 · 共 305 行 · 第 1/2 页

#define AT91C_LCDC_BYPASS     (0x1 << 0 ) /**< (LCDC) Bypass lcd_pccklk divider */
#define AT91C_LCDC_CLKVAL     (0x1FF << 12) /**< (LCDC) 9-bit Divider for pixel clock frequency */
#define AT91C_LCDC_LINCNT     (0x7FF << 21) /**< (LCDC) Line Counter (RO) */
/* --- Register LCDC_LCDCON2 */
#define AT91C_LCDC_DISTYPE    (0x3 << 0 ) /**< (LCDC) Display Type */
#define 	AT91C_LCDC_DISTYPE_STNMONO              0x0 /**< (LCDC) STN Mono */
#define 	AT91C_LCDC_DISTYPE_STNCOLOR             0x1 /**< (LCDC) STN Color */
#define 	AT91C_LCDC_DISTYPE_TFT                  0x2 /**< (LCDC) TFT */
#define AT91C_LCDC_SCANMOD    (0x1 << 2 ) /**< (LCDC) Scan Mode */
#define 	AT91C_LCDC_SCANMOD_SINGLESCAN           (0x0 <<  2) /**< (LCDC) Single Scan */
#define 	AT91C_LCDC_SCANMOD_DUALSCAN             (0x1 <<  2) /**< (LCDC) Dual Scan */
#define AT91C_LCDC_IFWIDTH    (0x3 << 3 ) /**< (LCDC) Interface Width */
#define 	AT91C_LCDC_IFWIDTH_FOURBITSWIDTH        (0x0 <<  3) /**< (LCDC) 4 Bits */
#define 	AT91C_LCDC_IFWIDTH_EIGTHBITSWIDTH       (0x1 <<  3) /**< (LCDC) 8 Bits */
#define 	AT91C_LCDC_IFWIDTH_SIXTEENBITSWIDTH     (0x2 <<  3) /**< (LCDC) 16 Bits */
#define AT91C_LCDC_PIXELSIZE  (0x7 << 5 ) /**< (LCDC) Bits per pixel */
#define 	AT91C_LCDC_PIXELSIZE_ONEBITSPERPIXEL      (0x0 <<  5) /**< (LCDC) 1 Bits */
#define 	AT91C_LCDC_PIXELSIZE_TWOBITSPERPIXEL      (0x1 <<  5) /**< (LCDC) 2 Bits */
#define 	AT91C_LCDC_PIXELSIZE_FOURBITSPERPIXEL     (0x2 <<  5) /**< (LCDC) 4 Bits */
#define 	AT91C_LCDC_PIXELSIZE_EIGTHBITSPERPIXEL    (0x3 <<  5) /**< (LCDC) 8 Bits */
#define 	AT91C_LCDC_PIXELSIZE_SIXTEENBITSPERPIXEL  (0x4 <<  5) /**< (LCDC) 16 Bits */
#define 	AT91C_LCDC_PIXELSIZE_TWENTYFOURBITSPERPIXEL (0x5 <<  5) /**< (LCDC) 24 Bits */
#define AT91C_LCDC_INVVD      (0x1 << 8 ) /**< (LCDC) lcd datas polarity */
#define 	AT91C_LCDC_INVVD_NORMALPOL            (0x0 <<  8) /**< (LCDC) Normal Polarity */
#define 	AT91C_LCDC_INVVD_INVERTEDPOL          (0x1 <<  8) /**< (LCDC) Inverted Polarity */
#define AT91C_LCDC_INVFRAME   (0x1 << 9 ) /**< (LCDC) lcd vsync polarity */
#define 	AT91C_LCDC_INVFRAME_NORMALPOL            (0x0 <<  9) /**< (LCDC) Normal Polarity */
#define 	AT91C_LCDC_INVFRAME_INVERTEDPOL          (0x1 <<  9) /**< (LCDC) Inverted Polarity */
#define AT91C_LCDC_INVLINE    (0x1 << 10) /**< (LCDC) lcd hsync polarity */
#define 	AT91C_LCDC_INVLINE_NORMALPOL            (0x0 << 10) /**< (LCDC) Normal Polarity */
#define 	AT91C_LCDC_INVLINE_INVERTEDPOL          (0x1 << 10) /**< (LCDC) Inverted Polarity */
#define AT91C_LCDC_INVCLK     (0x1 << 11) /**< (LCDC) lcd pclk polarity */
#define 	AT91C_LCDC_INVCLK_NORMALPOL            (0x0 << 11) /**< (LCDC) Normal Polarity */
#define 	AT91C_LCDC_INVCLK_INVERTEDPOL          (0x1 << 11) /**< (LCDC) Inverted Polarity */
#define AT91C_LCDC_INVDVAL    (0x1 << 12) /**< (LCDC) lcd dval polarity */
#define 	AT91C_LCDC_INVDVAL_NORMALPOL            (0x0 << 12) /**< (LCDC) Normal Polarity */
#define 	AT91C_LCDC_INVDVAL_INVERTEDPOL          (0x1 << 12) /**< (LCDC) Inverted Polarity */
#define AT91C_LCDC_CLKMOD     (0x1 << 15) /**< (LCDC) lcd pclk Mode */
#define 	AT91C_LCDC_CLKMOD_ACTIVEONLYDISP       (0x0 << 15) /**< (LCDC) Active during display period */
#define 	AT91C_LCDC_CLKMOD_ALWAYSACTIVE         (0x1 << 15) /**< (LCDC) Always Active */
#define AT91C_LCDC_MEMOR      (0x1 << 31) /**< (LCDC) lcd pclk Mode */
#define 	AT91C_LCDC_MEMOR_BIGIND               (0x0 << 31) /**< (LCDC) Big Endian */
#define 	AT91C_LCDC_MEMOR_LITTLEIND            (0x1 << 31) /**< (LCDC) Little Endian */
/* --- Register LCDC_TIM1 */
#define AT91C_LCDC_VFP        (0xFF << 0 ) /**< (LCDC) Vertical Front Porch */
#define AT91C_LCDC_VBP        (0xFF << 8 ) /**< (LCDC) Vertical Back Porch */
#define AT91C_LCDC_VPW        (0x3F << 16) /**< (LCDC) Vertical Synchronization Pulse Width */
#define AT91C_LCDC_VHDLY      (0xF << 24) /**< (LCDC) Vertical to Horizontal Delay */
/* --- Register LCDC_TIM2 */
#define AT91C_LCDC_HBP        (0xFF << 0 ) /**< (LCDC) Horizontal Back Porch */
#define AT91C_LCDC_HPW        (0x3F << 8 ) /**< (LCDC) Horizontal Synchronization Pulse Width */
#define AT91C_LCDC_HFP        (0x3FF << 22) /**< (LCDC) Horizontal Front Porch */
/* --- Register LCDC_LCDFRCFG */
#define AT91C_LCDC_LINEVAL    (0x7FF << 0 ) /**< (LCDC) Vertical Size of LCD Module */
#define AT91C_LCDC_HOZVAL     (0x7FF << 21) /**< (LCDC) Horizontal Size of LCD Module */
/* --- Register LCDC_FIFO */
#define AT91C_LCDC_FIFOTH     (0xFFFF << 0 ) /**< (LCDC) FIFO Threshold */
/* --- Register LCDC_MVAL */
#define AT91C_LCDC_MVALUE     (0xFF << 0 ) /**< (LCDC) Toggle Rate Value */
#define AT91C_LCDC_MMODE      (0x1 << 31) /**< (LCDC) Toggle Rate Sel */
#define 	AT91C_LCDC_MMODE_EACHFRAME            (0x0 << 31) /**< (LCDC) Each Frame */
#define 	AT91C_LCDC_MMODE_MVALDEFINED          (0x1 << 31) /**< (LCDC) Defined by MVAL */
/* --- Register LCDC_DP1_2 */
#define AT91C_LCDC_DP1_2_FIELD (0xFF << 0 ) /**< (LCDC) Ratio */
/* --- Register LCDC_DP4_7 */
#define AT91C_LCDC_DP4_7_FIELD (0xFFFFFFF << 0 ) /**< (LCDC) Ratio */
/* --- Register LCDC_DP3_5 */
#define AT91C_LCDC_DP3_5_FIELD (0xFFFFF << 0 ) /**< (LCDC) Ratio */
/* --- Register LCDC_DP2_3 */
#define AT91C_LCDC_DP2_3_FIELD (0xFFF << 0 ) /**< (LCDC) Ratio */
/* --- Register LCDC_DP5_7 */
#define AT91C_LCDC_DP5_7_FIELD (0xFFFFFFF << 0 ) /**< (LCDC) Ratio */
/* --- Register LCDC_DP3_4 */
#define AT91C_LCDC_DP3_4_FIELD (0xFFFF << 0 ) /**< (LCDC) Ratio */
/* --- Register LCDC_DP4_5 */
#define AT91C_LCDC_DP4_5_FIELD (0xFFFFF << 0 ) /**< (LCDC) Ratio */
/* --- Register LCDC_DP6_7 */
#define AT91C_LCDC_DP6_7_FIELD (0xFFFFFFF << 0 ) /**< (LCDC) Ratio */
/* --- Register LCDC_PWRCON */
#define AT91C_LCDC_PWR        (0x1 << 0 ) /**< (LCDC) LCD Module Power Control */
#define AT91C_LCDC_GUARDT     (0x7F << 1 ) /**< (LCDC) Delay in Frame Period */
#define AT91C_LCDC_BUSY       (0x1 << 31) /**< (LCDC) Read Only : 1 indicates that LCDC is busy */
#define 	AT91C_LCDC_BUSY_LCDNOTBUSY           (0x0 << 31) /**< (LCDC) LCD is Not Busy */
#define 	AT91C_LCDC_BUSY_LCDBUSY              (0x1 << 31) /**< (LCDC) LCD is Busy */
/* --- Register LCDC_CTRSTCON */
#define AT91C_LCDC_PS         (0x3 << 0 ) /**< (LCDC) LCD Contrast Counter Prescaler */
#define 	AT91C_LCDC_PS_NOTDIVIDED           0x0 /**< (LCDC) Counter Freq is System Freq. */
#define 	AT91C_LCDC_PS_DIVIDEDBYTWO         0x1 /**< (LCDC) Counter Freq is System Freq divided by 2. */
#define 	AT91C_LCDC_PS_DIVIDEDBYFOUR        0x2 /**< (LCDC) Counter Freq is System Freq divided by 4. */
#define 	AT91C_LCDC_PS_DIVIDEDBYEIGHT       0x3 /**< (LCDC) Counter Freq is System Freq divided by 8. */
#define AT91C_LCDC_POL        (0x1 << 2 ) /**< (LCDC) Polarity of output Pulse */
#define 	AT91C_LCDC_POL_NEGATIVEPULSE        (0x0 <<  2) /**< (LCDC) Negative Pulse */
#define 	AT91C_LCDC_POL_POSITIVEPULSE        (0x1 <<  2) /**< (LCDC) Positive Pulse */
#define AT91C_LCDC_ENA        (0x1 << 3 ) /**< (LCDC) PWM generator Control */
#define 	AT91C_LCDC_ENA_PWMGEMDISABLED       (0x0 <<  3) /**< (LCDC) PWM Generator Disabled */
#define 	AT91C_LCDC_ENA_PWMGEMENABLED        (0x1 <<  3) /**< (LCDC) PWM Generator Disabled */
/* --- Register LCDC_CTRSTVAL */
#define AT91C_LCDC_CVAL       (0xFF << 0 ) /**< (LCDC) PWM Compare Value */
/* --- Register LCDC_IER */
#define AT91C_LCDC_LNI        (0x1 << 0 ) /**< (LCDC) Line Interrupt */
#define AT91C_LCDC_LSTLNI     (0x1 << 1 ) /**< (LCDC) Last Line Interrupt */
#define AT91C_LCDC_EOFI       (0x1 << 2 ) /**< (LCDC) End Of Frame Interrupt */
#define AT91C_LCDC_UFLWI      (0x1 << 4 ) /**< (LCDC) FIFO Underflow Interrupt */
#define AT91C_LCDC_OWRI       (0x1 << 5 ) /**< (LCDC) Over Write Interrupt */
#define AT91C_LCDC_MERI       (0x1 << 6 ) /**< (LCDC) Memory Error  Interrupt */
/* --- Register LCDC_IDR */
#define AT91C_LCDC_LNI        (0x1 << 0 ) /**< (LCDC) Line Interrupt */
#define AT91C_LCDC_LSTLNI     (0x1 << 1 ) /**< (LCDC) Last Line Interrupt */
#define AT91C_LCDC_EOFI       (0x1 << 2 ) /**< (LCDC) End Of Frame Interrupt */
#define AT91C_LCDC_UFLWI      (0x1 << 4 ) /**< (LCDC) FIFO Underflow Interrupt */
#define AT91C_LCDC_OWRI       (0x1 << 5 ) /**< (LCDC) Over Write Interrupt */
#define AT91C_LCDC_MERI       (0x1 << 6 ) /**< (LCDC) Memory Error  Interrupt */
/* --- Register LCDC_IMR */
#define AT91C_LCDC_LNI        (0x1 << 0 ) /**< (LCDC) Line Interrupt */
#define AT91C_LCDC_LSTLNI     (0x1 << 1 ) /**< (LCDC) Last Line Interrupt */
#define AT91C_LCDC_EOFI       (0x1 << 2 ) /**< (LCDC) End Of Frame Interrupt */
#define AT91C_LCDC_UFLWI      (0x1 << 4 ) /**< (LCDC) FIFO Underflow Interrupt */
#define AT91C_LCDC_OWRI       (0x1 << 5 ) /**< (LCDC) Over Write Interrupt */
#define AT91C_LCDC_MERI       (0x1 << 6 ) /**< (LCDC) Memory Error  Interrupt */
/* --- Register LCDC_ISR */
#define AT91C_LCDC_LNI        (0x1 << 0 ) /**< (LCDC) Line Interrupt */
#define AT91C_LCDC_LSTLNI     (0x1 << 1 ) /**< (LCDC) Last Line Interrupt */
#define AT91C_LCDC_EOFI       (0x1 << 2 ) /**< (LCDC) End Of Frame Interrupt */
#define AT91C_LCDC_UFLWI      (0x1 << 4 ) /**< (LCDC) FIFO Underflow Interrupt */
#define AT91C_LCDC_OWRI       (0x1 << 5 ) /**< (LCDC) Over Write Interrupt */
#define AT91C_LCDC_MERI       (0x1 << 6 ) /**< (LCDC) Memory Error  Interrupt */
/* --- Register LCDC_ICR */
#define AT91C_LCDC_LNI        (0x1 << 0 ) /**< (LCDC) Line Interrupt */
#define AT91C_LCDC_LSTLNI     (0x1 << 1 ) /**< (LCDC) Last Line Interrupt */
#define AT91C_LCDC_EOFI       (0x1 << 2 ) /**< (LCDC) End Of Frame Interrupt */
#define AT91C_LCDC_UFLWI      (0x1 << 4 ) /**< (LCDC) FIFO Underflow Interrupt */
#define AT91C_LCDC_OWRI       (0x1 << 5 ) /**< (LCDC) Over Write Interrupt */
#define AT91C_LCDC_MERI       (0x1 << 6 ) /**< (LCDC) Memory Error  Interrupt */
/* --- Register LCDC_GPR */
#define AT91C_LCDC_GPRBUS     (0xFF << 0 ) /**< (LCDC) 8 bits available */
/* --- Register LCDC_ITR */
#define AT91C_LCDC_LNI        (0x1 << 0 ) /**< (LCDC) Line Interrupt */
#define AT91C_LCDC_LSTLNI     (0x1 << 1 ) /**< (LCDC) Last Line Interrupt */
#define AT91C_LCDC_EOFI       (0x1 << 2 ) /**< (LCDC) End Of Frame Interrupt */
#define AT91C_LCDC_UFLWI      (0x1 << 4 ) /**< (LCDC) FIFO Underflow Interrupt */
#define AT91C_LCDC_OWRI       (0x1 << 5 ) /**< (LCDC) Over Write Interrupt */
#define AT91C_LCDC_MERI       (0x1 << 6 ) /**< (LCDC) Memory Error  Interrupt */
/* --- Register LCDC_IRR */
#define AT91C_LCDC_LNI        (0x1 << 0 ) /**< (LCDC) Line Interrupt */
#define AT91C_LCDC_LSTLNI     (0x1 << 1 ) /**< (LCDC) Last Line Interrupt */
#define AT91C_LCDC_EOFI       (0x1 << 2 ) /**< (LCDC) End Of Frame Interrupt */
#define AT91C_LCDC_UFLWI      (0x1 << 4 ) /**< (LCDC) FIFO Underflow Interrupt */
#define AT91C_LCDC_OWRI       (0x1 << 5 ) /**< (LCDC) Over Write Interrupt */
#define AT91C_LCDC_MERI       (0x1 << 6 ) /**< (LCDC) Memory Error  Interrupt */

#endif /* __AT91SAM9263_LCDC_H */