at91sam9263_matrix.h

来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· C头文件 代码 · 共 323 行 · 第 1/2 页

#define 	AT91C_MATRIX_FIXED_DEFMSTR3_EMAC                 (0x7 << 18) /**< (MATRIX) EMAC Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR3_USB                  (0x8 << 18) /**< (MATRIX) USB Master is Default Master */
#define AT91C_MATRIX_ARBT     (0x3 << 24) /**< (MATRIX) Arbitration Type */
/* --- Register MATRIX_SCFG4 */
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0 ) /**< (MATRIX) Maximum Number of Allowed Cycles for a Burst */
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) /**< (MATRIX) Default Master Type */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           (0x0 << 16) /**< (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         (0x1 << 16) /**< (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        (0x2 << 16) /**< (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. */
#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) /**< (MATRIX) Fixed Index of Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I              (0x0 << 18) /**< (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D              (0x1 << 18) /**< (MATRIX) ARM926EJ-S Data Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR4_DMA                  (0x6 << 18) /**< (MATRIX) DMA Controller Master is Default Master */
#define AT91C_MATRIX_ARBT     (0x3 << 24) /**< (MATRIX) Arbitration Type */
/* --- Register MATRIX_SCFG5 */
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0 ) /**< (MATRIX) Maximum Number of Allowed Cycles for a Burst */
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) /**< (MATRIX) Default Master Type */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           (0x0 << 16) /**< (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         (0x1 << 16) /**< (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        (0x2 << 16) /**< (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. */
#define AT91C_MATRIX_FIXED_DEFMSTR5 (0x3 << 18) /**< (MATRIX) Fixed Index of Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR5_ARM926I              (0x0 << 18) /**< (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR5_ARM926D              (0x1 << 18) /**< (MATRIX) ARM926EJ-S Data Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR5_PDC                  (0x2 << 18) /**< (MATRIX) PDC Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR5_LCDC                 (0x3 << 18) /**< (MATRIX) LCDC Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR5_2DGC                 (0x4 << 18) /**< (MATRIX) 2DGC Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR5_ISI                  (0x5 << 18) /**< (MATRIX) ISI Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR5_DMA                  (0x6 << 18) /**< (MATRIX) DMA Controller Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR5_EMAC                 (0x7 << 18) /**< (MATRIX) EMAC Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR5_USB                  (0x8 << 18) /**< (MATRIX) USB Master is Default Master */
#define AT91C_MATRIX_ARBT     (0x3 << 24) /**< (MATRIX) Arbitration Type */
/* --- Register MATRIX_SCFG6 */
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0 ) /**< (MATRIX) Maximum Number of Allowed Cycles for a Burst */
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) /**< (MATRIX) Default Master Type */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           (0x0 << 16) /**< (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         (0x1 << 16) /**< (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        (0x2 << 16) /**< (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. */
#define AT91C_MATRIX_FIXED_DEFMSTR6 (0x3 << 18) /**< (MATRIX) Fixed Index of Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR6_ARM926I              (0x0 << 18) /**< (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR6_ARM926D              (0x1 << 18) /**< (MATRIX) ARM926EJ-S Data Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR6_PDC                  (0x2 << 18) /**< (MATRIX) PDC Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR6_LCDC                 (0x3 << 18) /**< (MATRIX) LCDC Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR6_2DGC                 (0x4 << 18) /**< (MATRIX) 2DGC Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR6_ISI                  (0x5 << 18) /**< (MATRIX) ISI Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR6_DMA                  (0x6 << 18) /**< (MATRIX) DMA Controller Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR6_EMAC                 (0x7 << 18) /**< (MATRIX) EMAC Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR6_USB                  (0x8 << 18) /**< (MATRIX) USB Master is Default Master */
#define AT91C_MATRIX_ARBT     (0x3 << 24) /**< (MATRIX) Arbitration Type */
/* --- Register MATRIX_SCFG7 */
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0 ) /**< (MATRIX) Maximum Number of Allowed Cycles for a Burst */
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) /**< (MATRIX) Default Master Type */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR           (0x0 << 16) /**< (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR         (0x1 << 16) /**< (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. */
#define 	AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR        (0x2 << 16) /**< (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. */
#define AT91C_MATRIX_FIXED_DEFMSTR7 (0x3 << 18) /**< (MATRIX) Fixed Index of Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR7_ARM926I              (0x0 << 18) /**< (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR7_ARM926D              (0x1 << 18) /**< (MATRIX) ARM926EJ-S Data Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR7_PDC                  (0x2 << 18) /**< (MATRIX) PDC Master is Default Master */
#define 	AT91C_MATRIX_FIXED_DEFMSTR7_DMA                  (0x6 << 18) /**< (MATRIX) DMA Controller Master is Default Master */
#define AT91C_MATRIX_ARBT     (0x3 << 24) /**< (MATRIX) Arbitration Type */
/* --- Register MATRIX_PRAS0 */
#define AT91C_MATRIX_M0PR     (0x3 << 0 ) /**< (MATRIX) ARM926EJ-S Instruction priority */
#define AT91C_MATRIX_M1PR     (0x3 << 4 ) /**< (MATRIX) ARM926EJ-S Data priority */
#define AT91C_MATRIX_M2PR     (0x3 << 8 ) /**< (MATRIX) PDC priority */
#define AT91C_MATRIX_M3PR     (0x3 << 12) /**< (MATRIX) LCDC priority */
#define AT91C_MATRIX_M4PR     (0x3 << 16) /**< (MATRIX) 2DGC priority */
#define AT91C_MATRIX_M5PR     (0x3 << 20) /**< (MATRIX) ISI priority */
#define AT91C_MATRIX_M6PR     (0x3 << 24) /**< (MATRIX) DMA priority */
#define AT91C_MATRIX_M7PR     (0x3 << 28) /**< (MATRIX) EMAC priority */
/* --- Register MATRIX_PRBS0 */
#define AT91C_MATRIX_M8PR     (0x3 << 0 ) /**< (MATRIX) USB priority */
/* --- Register MATRIX_PRAS1 */
#define AT91C_MATRIX_M0PR     (0x3 << 0 ) /**< (MATRIX) ARM926EJ-S Instruction priority */
#define AT91C_MATRIX_M1PR     (0x3 << 4 ) /**< (MATRIX) ARM926EJ-S Data priority */
#define AT91C_MATRIX_M2PR     (0x3 << 8 ) /**< (MATRIX) PDC priority */
#define AT91C_MATRIX_M3PR     (0x3 << 12) /**< (MATRIX) LCDC priority */
#define AT91C_MATRIX_M4PR     (0x3 << 16) /**< (MATRIX) 2DGC priority */
#define AT91C_MATRIX_M5PR     (0x3 << 20) /**< (MATRIX) ISI priority */
#define AT91C_MATRIX_M6PR     (0x3 << 24) /**< (MATRIX) DMA priority */
#define AT91C_MATRIX_M7PR     (0x3 << 28) /**< (MATRIX) EMAC priority */
/* --- Register MATRIX_PRBS1 */
#define AT91C_MATRIX_M8PR     (0x3 << 0 ) /**< (MATRIX) USB priority */
/* --- Register MATRIX_PRAS2 */
#define AT91C_MATRIX_M0PR     (0x3 << 0 ) /**< (MATRIX) ARM926EJ-S Instruction priority */
#define AT91C_MATRIX_M1PR     (0x3 << 4 ) /**< (MATRIX) ARM926EJ-S Data priority */
#define AT91C_MATRIX_M2PR     (0x3 << 8 ) /**< (MATRIX) PDC priority */
#define AT91C_MATRIX_M3PR     (0x3 << 12) /**< (MATRIX) LCDC priority */
#define AT91C_MATRIX_M4PR     (0x3 << 16) /**< (MATRIX) 2DGC priority */
#define AT91C_MATRIX_M5PR     (0x3 << 20) /**< (MATRIX) ISI priority */
#define AT91C_MATRIX_M6PR     (0x3 << 24) /**< (MATRIX) DMA priority */
#define AT91C_MATRIX_M7PR     (0x3 << 28) /**< (MATRIX) EMAC priority */
/* --- Register MATRIX_PRBS2 */
#define AT91C_MATRIX_M8PR     (0x3 << 0 ) /**< (MATRIX) USB priority */
/* --- Register MATRIX_PRAS3 */
#define AT91C_MATRIX_M0PR     (0x3 << 0 ) /**< (MATRIX) ARM926EJ-S Instruction priority */
#define AT91C_MATRIX_M1PR     (0x3 << 4 ) /**< (MATRIX) ARM926EJ-S Data priority */
#define AT91C_MATRIX_M2PR     (0x3 << 8 ) /**< (MATRIX) PDC priority */
#define AT91C_MATRIX_M3PR     (0x3 << 12) /**< (MATRIX) LCDC priority */
#define AT91C_MATRIX_M4PR     (0x3 << 16) /**< (MATRIX) 2DGC priority */
#define AT91C_MATRIX_M5PR     (0x3 << 20) /**< (MATRIX) ISI priority */
#define AT91C_MATRIX_M6PR     (0x3 << 24) /**< (MATRIX) DMA priority */
#define AT91C_MATRIX_M7PR     (0x3 << 28) /**< (MATRIX) EMAC priority */
/* --- Register MATRIX_PRBS3 */
#define AT91C_MATRIX_M8PR     (0x3 << 0 ) /**< (MATRIX) USB priority */
/* --- Register MATRIX_PRAS4 */
#define AT91C_MATRIX_M0PR     (0x3 << 0 ) /**< (MATRIX) ARM926EJ-S Instruction priority */
#define AT91C_MATRIX_M1PR     (0x3 << 4 ) /**< (MATRIX) ARM926EJ-S Data priority */
#define AT91C_MATRIX_M2PR     (0x3 << 8 ) /**< (MATRIX) PDC priority */
#define AT91C_MATRIX_M3PR     (0x3 << 12) /**< (MATRIX) LCDC priority */
#define AT91C_MATRIX_M4PR     (0x3 << 16) /**< (MATRIX) 2DGC priority */
#define AT91C_MATRIX_M5PR     (0x3 << 20) /**< (MATRIX) ISI priority */
#define AT91C_MATRIX_M6PR     (0x3 << 24) /**< (MATRIX) DMA priority */
#define AT91C_MATRIX_M7PR     (0x3 << 28) /**< (MATRIX) EMAC priority */
/* --- Register MATRIX_PRBS4 */
#define AT91C_MATRIX_M8PR     (0x3 << 0 ) /**< (MATRIX) USB priority */
/* --- Register MATRIX_PRAS5 */
#define AT91C_MATRIX_M0PR     (0x3 << 0 ) /**< (MATRIX) ARM926EJ-S Instruction priority */
#define AT91C_MATRIX_M1PR     (0x3 << 4 ) /**< (MATRIX) ARM926EJ-S Data priority */
#define AT91C_MATRIX_M2PR     (0x3 << 8 ) /**< (MATRIX) PDC priority */
#define AT91C_MATRIX_M3PR     (0x3 << 12) /**< (MATRIX) LCDC priority */
#define AT91C_MATRIX_M4PR     (0x3 << 16) /**< (MATRIX) 2DGC priority */
#define AT91C_MATRIX_M5PR     (0x3 << 20) /**< (MATRIX) ISI priority */
#define AT91C_MATRIX_M6PR     (0x3 << 24) /**< (MATRIX) DMA priority */
#define AT91C_MATRIX_M7PR     (0x3 << 28) /**< (MATRIX) EMAC priority */
/* --- Register MATRIX_PRBS5 */
#define AT91C_MATRIX_M8PR     (0x3 << 0 ) /**< (MATRIX) USB priority */
/* --- Register MATRIX_PRAS6 */
#define AT91C_MATRIX_M0PR     (0x3 << 0 ) /**< (MATRIX) ARM926EJ-S Instruction priority */
#define AT91C_MATRIX_M1PR     (0x3 << 4 ) /**< (MATRIX) ARM926EJ-S Data priority */
#define AT91C_MATRIX_M2PR     (0x3 << 8 ) /**< (MATRIX) PDC priority */
#define AT91C_MATRIX_M3PR     (0x3 << 12) /**< (MATRIX) LCDC priority */
#define AT91C_MATRIX_M4PR     (0x3 << 16) /**< (MATRIX) 2DGC priority */
#define AT91C_MATRIX_M5PR     (0x3 << 20) /**< (MATRIX) ISI priority */
#define AT91C_MATRIX_M6PR     (0x3 << 24) /**< (MATRIX) DMA priority */
#define AT91C_MATRIX_M7PR     (0x3 << 28) /**< (MATRIX) EMAC priority */
/* --- Register MATRIX_PRBS6 */
#define AT91C_MATRIX_M8PR     (0x3 << 0 ) /**< (MATRIX) USB priority */
/* --- Register MATRIX_PRAS7 */
#define AT91C_MATRIX_M0PR     (0x3 << 0 ) /**< (MATRIX) ARM926EJ-S Instruction priority */
#define AT91C_MATRIX_M1PR     (0x3 << 4 ) /**< (MATRIX) ARM926EJ-S Data priority */
#define AT91C_MATRIX_M2PR     (0x3 << 8 ) /**< (MATRIX) PDC priority */
#define AT91C_MATRIX_M3PR     (0x3 << 12) /**< (MATRIX) LCDC priority */
#define AT91C_MATRIX_M4PR     (0x3 << 16) /**< (MATRIX) 2DGC priority */
#define AT91C_MATRIX_M5PR     (0x3 << 20) /**< (MATRIX) ISI priority */
#define AT91C_MATRIX_M6PR     (0x3 << 24) /**< (MATRIX) DMA priority */
#define AT91C_MATRIX_M7PR     (0x3 << 28) /**< (MATRIX) EMAC priority */
/* --- Register MATRIX_PRBS7 */
#define AT91C_MATRIX_M8PR     (0x3 << 0 ) /**< (MATRIX) USB priority */
/* --- Register MATRIX_MRCR */
#define AT91C_MATRIX_RCA926I  (0x1 << 0 ) /**< (MATRIX) Remap Command Bit for ARM926EJ-S Instruction */
#define AT91C_MATRIX_RCA926D  (0x1 << 1 ) /**< (MATRIX) Remap Command Bit for ARM926EJ-S Data */
#define AT91C_MATRIX_RCB2     (0x1 << 2 ) /**< (MATRIX) Remap Command Bit for PDC */
#define AT91C_MATRIX_RCB3     (0x1 << 3 ) /**< (MATRIX) Remap Command Bit for LCD */
#define AT91C_MATRIX_RCB4     (0x1 << 4 ) /**< (MATRIX) Remap Command Bit for 2DGC */
#define AT91C_MATRIX_RCB5     (0x1 << 5 ) /**< (MATRIX) Remap Command Bit for ISI */
#define AT91C_MATRIX_RCB6     (0x1 << 6 ) /**< (MATRIX) Remap Command Bit for DMA */
#define AT91C_MATRIX_RCB7     (0x1 << 7 ) /**< (MATRIX) Remap Command Bit for EMAC */
#define AT91C_MATRIX_RCB8     (0x1 << 8 ) /**< (MATRIX) Remap Command Bit for USB */

#endif /* __AT91SAM9263_MATRIX_H */