at91sam9263_matrix.h
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/* linux/include/asm-arm/arch-at91sam9263/at91sam9263_matrix.h
*
* Hardware definition for the matrix peripheral in the ATMEL at91sam9263 processor
*
* Generated 12/07/2006 (13:13:46) AT91 SW Application Group from HMATRIX1_SAM9262 V1.10
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __AT91SAM9263_MATRIX_H
#define __AT91SAM9263_MATRIX_H
/* -------------------------------------------------------- */
/* MATRIX ID definitions for AT91SAM9263 */
/* -------------------------------------------------------- */
/* -------------------------------------------------------- */
/* MATRIX Base Address definitions for AT91SAM9263 */
/* -------------------------------------------------------- */
#define AT91C_BASE_MATRIX 0xFFFFEC00 /**< MATRIX base address */
/* -------------------------------------------------------- */
/* PIO definition for MATRIX hardware peripheral */
/* -------------------------------------------------------- */
/* -------------------------------------------------------- */
/* Register offset definition for MATRIX hardware peripheral */
/* -------------------------------------------------------- */
#define MATRIX_MCFG0 (0x0000) /**< Master Configuration Register 0 */
#define MATRIX_MCFG1 (0x0004) /**< Master Configuration Register 1 */
#define MATRIX_MCFG2 (0x0008) /**< Master Configuration Register 2 */
#define MATRIX_MCFG3 (0x000C) /**< Master Configuration Register 3 */
#define MATRIX_MCFG4 (0x0010) /**< Master Configuration Register 4 */
#define MATRIX_MCFG5 (0x0014) /**< Master Configuration Register 5 */
#define MATRIX_MCFG6 (0x0018) /**< Master Configuration Register 6 */
#define MATRIX_MCFG7 (0x001C) /**< Master Configuration Register 7 */
#define MATRIX_MCFG8 (0x0020) /**< Master Configuration Register 8 */
#define MATRIX_SCFG0 (0x0040) /**< Slave Configuration Register 0 */
#define MATRIX_SCFG1 (0x0044) /**< Slave Configuration Register 1 */
#define MATRIX_SCFG2 (0x0048) /**< Slave Configuration Register 2 */
#define MATRIX_SCFG3 (0x004C) /**< Slave Configuration Register 3 */
#define MATRIX_SCFG4 (0x0050) /**< Slave Configuration Register 4 */
#define MATRIX_SCFG5 (0x0054) /**< Slave Configuration Register 5 */
#define MATRIX_SCFG6 (0x0058) /**< Slave Configuration Register 6 */
#define MATRIX_SCFG7 (0x005C) /**< Slave Configuration Register 7 */
#define MATRIX_PRAS0 (0x0080) /**< PRAS0 */
#define MATRIX_PRBS0 (0x0084) /**< PRBS0 */
#define MATRIX_PRAS1 (0x0088) /**< PRAS1 */
#define MATRIX_PRBS1 (0x008C) /**< PRBS1 */
#define MATRIX_PRAS2 (0x0090) /**< PRAS2 */
#define MATRIX_PRBS2 (0x0094) /**< PRBS2 */
#define MATRIX_PRAS3 (0x0098) /**< PRAS3 */
#define MATRIX_PRBS3 (0x009C) /**< PRBS3 */
#define MATRIX_PRAS4 (0x00A0) /**< PRAS4 */
#define MATRIX_PRBS4 (0x00A4) /**< PRBS4 */
#define MATRIX_PRAS5 (0x00A8) /**< PRAS5 */
#define MATRIX_PRBS5 (0x00AC) /**< PRBS5 */
#define MATRIX_PRAS6 (0x00B0) /**< PRAS6 */
#define MATRIX_PRBS6 (0x00B4) /**< PRBS6 */
#define MATRIX_PRAS7 (0x00B8) /**< PRAS7 */
#define MATRIX_PRBS7 (0x00BC) /**< PRBS7 */
#define MATRIX_MRCR (0x0100) /**< Master Remp Control Register */
/* -------------------------------------------------------- */
/* Bitfields definition for MATRIX hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register MATRIX_MCFG0 */
#define AT91C_MATRIX_ULBT (0x7 << 0 ) /**< (MATRIX) Undefined Length Burst Type */
/* --- Register MATRIX_MCFG1 */
#define AT91C_MATRIX_ULBT (0x7 << 0 ) /**< (MATRIX) Undefined Length Burst Type */
/* --- Register MATRIX_MCFG2 */
#define AT91C_MATRIX_ULBT (0x7 << 0 ) /**< (MATRIX) Undefined Length Burst Type */
/* --- Register MATRIX_MCFG3 */
#define AT91C_MATRIX_ULBT (0x7 << 0 ) /**< (MATRIX) Undefined Length Burst Type */
/* --- Register MATRIX_MCFG4 */
#define AT91C_MATRIX_ULBT (0x7 << 0 ) /**< (MATRIX) Undefined Length Burst Type */
/* --- Register MATRIX_MCFG5 */
#define AT91C_MATRIX_ULBT (0x7 << 0 ) /**< (MATRIX) Undefined Length Burst Type */
/* --- Register MATRIX_MCFG6 */
#define AT91C_MATRIX_ULBT (0x7 << 0 ) /**< (MATRIX) Undefined Length Burst Type */
/* --- Register MATRIX_MCFG7 */
#define AT91C_MATRIX_ULBT (0x7 << 0 ) /**< (MATRIX) Undefined Length Burst Type */
/* --- Register MATRIX_MCFG8 */
#define AT91C_MATRIX_ULBT (0x7 << 0 ) /**< (MATRIX) Undefined Length Burst Type */
/* --- Register MATRIX_SCFG0 */
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0 ) /**< (MATRIX) Maximum Number of Allowed Cycles for a Burst */
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) /**< (MATRIX) Default Master Type */
#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) /**< (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. */
#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) /**< (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. */
#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) /**< (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. */
#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) /**< (MATRIX) Fixed Index of Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) /**< (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) /**< (MATRIX) ARM926EJ-S Data Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR0_PDC (0x2 << 18) /**< (MATRIX) PDC Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) /**< (MATRIX) LCDC Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR0_2DGC (0x4 << 18) /**< (MATRIX) 2DGC Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR0_ISI (0x5 << 18) /**< (MATRIX) ISI Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR0_DMA (0x6 << 18) /**< (MATRIX) DMA Controller Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR0_EMAC (0x7 << 18) /**< (MATRIX) EMAC Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR0_USB (0x8 << 18) /**< (MATRIX) USB Master is Default Master */
#define AT91C_MATRIX_ARBT (0x3 << 24) /**< (MATRIX) Arbitration Type */
/* --- Register MATRIX_SCFG1 */
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0 ) /**< (MATRIX) Maximum Number of Allowed Cycles for a Burst */
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) /**< (MATRIX) Default Master Type */
#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) /**< (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. */
#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) /**< (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. */
#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) /**< (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. */
#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) /**< (MATRIX) Fixed Index of Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) /**< (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) /**< (MATRIX) ARM926EJ-S Data Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR1_PDC (0x2 << 18) /**< (MATRIX) PDC Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) /**< (MATRIX) LCDC Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR1_2DGC (0x4 << 18) /**< (MATRIX) 2DGC Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR1_ISI (0x5 << 18) /**< (MATRIX) ISI Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR1_DMA (0x6 << 18) /**< (MATRIX) DMA Controller Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR1_EMAC (0x7 << 18) /**< (MATRIX) EMAC Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR1_USB (0x8 << 18) /**< (MATRIX) USB Master is Default Master */
#define AT91C_MATRIX_ARBT (0x3 << 24) /**< (MATRIX) Arbitration Type */
/* --- Register MATRIX_SCFG2 */
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0 ) /**< (MATRIX) Maximum Number of Allowed Cycles for a Burst */
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) /**< (MATRIX) Default Master Type */
#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) /**< (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. */
#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) /**< (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. */
#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) /**< (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. */
#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) /**< (MATRIX) Fixed Index of Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) /**< (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) /**< (MATRIX) ARM926EJ-S Data Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR2_DMA (0x6 << 18) /**< (MATRIX) DMA Controller Master is Default Master */
#define AT91C_MATRIX_ARBT (0x3 << 24) /**< (MATRIX) Arbitration Type */
/* --- Register MATRIX_SCFG3 */
#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0 ) /**< (MATRIX) Maximum Number of Allowed Cycles for a Burst */
#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) /**< (MATRIX) Default Master Type */
#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) /**< (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. */
#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) /**< (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. */
#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) /**< (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. */
#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) /**< (MATRIX) Fixed Index of Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) /**< (MATRIX) ARM926EJ-S Instruction Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) /**< (MATRIX) ARM926EJ-S Data Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR3_PDC (0x2 << 18) /**< (MATRIX) PDC Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) /**< (MATRIX) LCDC Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR3_2DGC (0x4 << 18) /**< (MATRIX) 2DGC Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR3_ISI (0x5 << 18) /**< (MATRIX) ISI Master is Default Master */
#define AT91C_MATRIX_FIXED_DEFMSTR3_DMA (0x6 << 18) /**< (MATRIX) DMA Controller Master is Default Master */
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