at91sam9263_emac.h

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/* linux/include/asm-arm/arch-at91sam9263/at91sam9263_emac.h
 * 
 * Hardware definition for the emac peripheral in the ATMEL at91sam9263 processor
 * 
 * Generated  12/07/2006 (13:13:46) AT91 SW Application Group from EMACB_6119A V1.6
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */


#ifndef __AT91SAM9263_EMAC_H
#define __AT91SAM9263_EMAC_H

/* -------------------------------------------------------- */
/* EMAC ID definitions for  AT91SAM9263           */
/* -------------------------------------------------------- */
#ifndef AT91C_ID_EMAC
#define AT91C_ID_EMAC  	21 /**< Ethernet Mac id */
#endif /* AT91C_ID_EMAC */

/* -------------------------------------------------------- */
/* EMAC Base Address definitions for  AT91SAM9263   */
/* -------------------------------------------------------- */
#define AT91C_BASE_MACB      	0xFFFBC000 /**< MACB base address */

/* -------------------------------------------------------- */
/* PIO definition for EMAC hardware peripheral */
/* -------------------------------------------------------- */
#define AT91C_PC26_ECOL     	(1 << 26) /**<  */
#define AT91C_PE22_ECRS     	(1 << 22) /**<  */
#define AT91C_PE31_EF100    	(1 << 31) /**<  */
#define AT91C_PE29_EMDC     	(1 << 29) /**<  */
#define AT91C_PE30_EMDIO    	(1 << 30) /**<  */
#define AT91C_PE25_ERX0     	(1 << 25) /**<  */
#define AT91C_PE26_ERX1     	(1 << 26) /**<  */
#define AT91C_PC22_ERX2     	(1 << 22) /**<  */
#define AT91C_PC23_ERX3     	(1 << 23) /**<  */
#define AT91C_PC27_ERXCK    	(1 << 27) /**<  */
#define AT91C_PC25_ERXDV    	(1 << 25) /**<  */
#define AT91C_PE27_ERXER    	(1 << 27) /**<  */
#define AT91C_PE23_ETX0     	(1 << 23) /**<  */
#define AT91C_PE24_ETX1     	(1 << 24) /**<  */
#define AT91C_PC20_ETX2     	(1 << 20) /**<  */
#define AT91C_PC21_ETX3     	(1 << 21) /**<  */
#define AT91C_PE21_ETXCK    	(1 << 21) /**<  */
#define AT91C_PE28_ETXEN    	(1 << 28) /**<  */
#define AT91C_PC24_ETXER    	(1 << 24) /**<  */


/* -------------------------------------------------------- */
/* Register offset definition for EMAC hardware peripheral */
/* -------------------------------------------------------- */
#define EMAC_NCR 	(0x0000) 	/**< Network Control Register */
#define EMAC_NCFGR 	(0x0004) 	/**< Network Configuration Register */
#define EMAC_NSR 	(0x0008) 	/**< Network Status Register */
#define EMAC_TSR 	(0x0014) 	/**< Transmit Status Register */
#define EMAC_RBQP 	(0x0018) 	/**< Receive Buffer Queue Pointer */
#define EMAC_TBQP 	(0x001C) 	/**< Transmit Buffer Queue Pointer */
#define EMAC_RSR 	(0x0020) 	/**< Receive Status Register */
#define EMAC_ISR 	(0x0024) 	/**< Interrupt Status Register */
#define EMAC_IER 	(0x0028) 	/**< Interrupt Enable Register */
#define EMAC_IDR 	(0x002C) 	/**< Interrupt Disable Register */
#define EMAC_IMR 	(0x0030) 	/**< Interrupt Mask Register */
#define EMAC_MAN 	(0x0034) 	/**< PHY Maintenance Register */
#define EMAC_PTR 	(0x0038) 	/**< Pause Time Register */
#define EMAC_PFR 	(0x003C) 	/**< Pause Frames received Register */
#define EMAC_FTO 	(0x0040) 	/**< Frames Transmitted OK Register */
#define EMAC_SCF 	(0x0044) 	/**< Single Collision Frame Register */
#define EMAC_MCF 	(0x0048) 	/**< Multiple Collision Frame Register */
#define EMAC_FRO 	(0x004C) 	/**< Frames Received OK Register */
#define EMAC_FCSE 	(0x0050) 	/**< Frame Check Sequence Error Register */
#define EMAC_ALE 	(0x0054) 	/**< Alignment Error Register */
#define EMAC_DTF 	(0x0058) 	/**< Deferred Transmission Frame Register */
#define EMAC_LCOL 	(0x005C) 	/**< Late Collision Register */
#define EMAC_ECOL 	(0x0060) 	/**< Excessive Collision Register */
#define EMAC_TUND 	(0x0064) 	/**< Transmit Underrun Error Register */
#define EMAC_CSE 	(0x0068) 	/**< Carrier Sense Error Register */
#define EMAC_RRE 	(0x006C) 	/**< Receive Ressource Error Register */
#define EMAC_ROV 	(0x0070) 	/**< Receive Overrun Errors Register */
#define EMAC_RSE 	(0x0074) 	/**< Receive Symbol Errors Register */
#define EMAC_ELE 	(0x0078) 	/**< Excessive Length Errors Register */
#define EMAC_RJA 	(0x007C) 	/**< Receive Jabbers Register */
#define EMAC_USF 	(0x0080) 	/**< Undersize Frames Register */
#define EMAC_STE 	(0x0084) 	/**< SQE Test Error Register */
#define EMAC_RLE 	(0x0088) 	/**< Receive Length Field Mismatch Register */
#define EMAC_TPF 	(0x008C) 	/**< Transmitted Pause Frames Register */
#define EMAC_HRB 	(0x0090) 	/**< Hash Address Bottom[31:0] */
#define EMAC_HRT 	(0x0094) 	/**< Hash Address Top[63:32] */
#define EMAC_SA1L 	(0x0098) 	/**< Specific Address 1 Bottom, First 4 bytes */
#define EMAC_SA1H 	(0x009C) 	/**< Specific Address 1 Top, Last 2 bytes */
#define EMAC_SA2L 	(0x00A0) 	/**< Specific Address 2 Bottom, First 4 bytes */
#define EMAC_SA2H 	(0x00A4) 	/**< Specific Address 2 Top, Last 2 bytes */
#define EMAC_SA3L 	(0x00A8) 	/**< Specific Address 3 Bottom, First 4 bytes */
#define EMAC_SA3H 	(0x00AC) 	/**< Specific Address 3 Top, Last 2 bytes */
#define EMAC_SA4L 	(0x00B0) 	/**< Specific Address 4 Bottom, First 4 bytes */
#define EMAC_SA4H 	(0x00B4) 	/**< Specific Address 4 Top, Last 2 bytes */
#define EMAC_TID 	(0x00B8) 	/**< Type ID Checking Register */
#define EMAC_TPQ 	(0x00BC) 	/**< Transmit Pause Quantum Register */
#define EMAC_USRIO 	(0x00C0) 	/**< USER Input/Output Register */
#define EMAC_WOL 	(0x00C4) 	/**< Wake On LAN Register */
#define EMAC_REV 	(0x00FC) 	/**< Revision Register */

/* -------------------------------------------------------- */
/* Bitfields definition for EMAC hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register EMAC_NCR */
#define AT91C_EMAC_LB         (0x1 << 0 ) /**< (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
#define AT91C_EMAC_LLB        (0x1 << 1 ) /**< (EMAC) Loopback local.  */
#define AT91C_EMAC_RE         (0x1 << 2 ) /**< (EMAC) Receive enable.  */
#define AT91C_EMAC_TE         (0x1 << 3 ) /**< (EMAC) Transmit enable.  */
#define AT91C_EMAC_MPE        (0x1 << 4 ) /**< (EMAC) Management port enable.  */