at91sam9263_dma.h

最新版IAR FOR ARM（EWARM）5.11中的代码例子

#define AT91C_DMA_DS_HS_POL   (0x1 << 18) /**< (DMA) Destination Handshaking Interface Polarity */
#define AT91C_DMA_SR_HS_POL   (0x1 << 19) /**< (DMA) Source Handshaking Interface Polarity */
#define AT91C_DMA_MAX_ABRST   (0x3FF << 20) /**< (DMA) Maximum AMBA Burst Length */
#define AT91C_DMA_RELOAD_SR   (0x1 << 30) /**< (DMA) Automatic Source Reload */
#define AT91C_DMA_RELOAD_DS   (0x1 << 31) /**< (DMA) Automatic Destination Reload */
/* --- Register DMA_CFGh */
#define AT91C_DMA_FCMODE      (0x1 << 0 ) /**< (DMA) Flow Control Mode */
#define AT91C_DMA_FIFO_MODE   (0x1 << 1 ) /**< (DMA) Fifo Mode Select */
#define AT91C_DMA_PROTCTL     (0x7 << 2 ) /**< (DMA) Protection Control */
#define AT91C_DMA_DS_UPD_EN   (0x1 << 5 ) /**< (DMA) Destination Status Update Enable */
#define AT91C_DMA_SS_UPD_EN   (0x1 << 6 ) /**< (DMA) Source Status Update Enable */
#define AT91C_DMA_SRC_PER     (0xF << 7 ) /**< (DMA) Source Hardware Handshaking Interface */
#define AT91C_DMA_DEST_PER    (0xF << 11) /**< (DMA) Destination Hardware Handshaking Interface */
/* --- Register DMA_SGR */
#define AT91C_DMA_SGI         (0xFFFFF << 0 ) /**< (DMA) Source Gather Interval */
#define AT91C_DMA_SGC         (0xFFF << 20) /**< (DMA) Source Gather Count */
/* --- Register DMA_DSR */
#define AT91C_DMA_DSI         (0xFFFFF << 0 ) /**< (DMA) Destination Scatter Interval */
#define AT91C_DMA_DSC         (0xFFF << 20) /**< (DMA) Destination Scatter Count */
/* --- Register DMA_SAR */
#define AT91C_DMA_SADD        (0x0 << 0 ) /**< (DMA) Source Address of DMA Transfer */
/* --- Register DMA_DAR */
#define AT91C_DMA_DADD        (0x0 << 0 ) /**< (DMA) Destination Address of DMA Transfer */
/* --- Register DMA_LLP */
#define AT91C_DMA_LOC         (0x0 << 0 ) /**< (DMA) Address of the Next LLI */
/* --- Register DMA_CTLl */
#define AT91C_DMA_INT_EN      (0x1 << 0 ) /**< (DMA) Interrupt Enable Bit */
#define AT91C_DMA_DST_TR_WIDTH (0x7 << 1 ) /**< (DMA) Destination Transfer Width */
#define AT91C_DMA_SRC_TR_WIDTH (0x7 << 4 ) /**< (DMA) Source Transfer Width */
#define AT91C_DMA_DINC        (0x3 << 7 ) /**< (DMA) Destination Address Increment */
#define AT91C_DMA_SINC        (0x3 << 9 ) /**< (DMA) Source Address Increment */
#define AT91C_DMA_DEST_MSIZE  (0x7 << 11) /**< (DMA) Destination Burst Transaction Length */
#define AT91C_DMA_SRC_MSIZE   (0x7 << 14) /**< (DMA) Source Burst Transaction Length */
#define AT91C_DMA_S_GATH_EN   (0x1 << 17) /**< (DMA) Source Gather Enable Bit */
#define AT91C_DMA_D_SCAT_EN   (0x1 << 18) /**< (DMA) Destination Scatter Enable Bit */
#define AT91C_DMA_TT_FC       (0x7 << 20) /**< (DMA) Transfer Type and Flow Control */
#define AT91C_DMA_DMS         (0x3 << 23) /**< (DMA) Destination Master Select */
#define AT91C_DMA_SMS         (0x3 << 25) /**< (DMA) Source Master Select */
#define AT91C_DMA_LLP_D_EN    (0x1 << 27) /**< (DMA) Destination Block Chaining Enable */
#define AT91C_DMA_LLP_S_EN    (0x1 << 28) /**< (DMA) Source Block Chaining Enable */
/* --- Register DMA_CTLh */
#define AT91C_DMA_BLOCK_TS    (0xFFF << 0 ) /**< (DMA) Block Transfer Size */
#define AT91C_DMA_DONE        (0x1 << 12) /**< (DMA) Done bit */
/* --- Register DMA_CFGl */
#define AT91C_DMA_CH_PRIOR    (0x7 << 5 ) /**< (DMA) Channel Priority */
#define AT91C_DMA_CH_SUSP     (0x1 << 8 ) /**< (DMA) Channel Suspend */
#define AT91C_DMA_FIFO_EMPT   (0x1 << 9 ) /**< (DMA) Fifo Empty */
#define AT91C_DMA_HS_SEL_DS   (0x1 << 10) /**< (DMA) Destination Software or Hardware Handshaking Select */
#define AT91C_DMA_HS_SEL_SR   (0x1 << 11) /**< (DMA) Source Software or Hardware Handshaking Select */
#define AT91C_DMA_LOCK_CH_L   (0x3 << 12) /**< (DMA) Channel Lock Level */
#define AT91C_DMA_LOCK_B_L    (0x3 << 14) /**< (DMA) Bus Lock Level */
#define AT91C_DMA_LOCK_CH     (0x1 << 16) /**< (DMA) Channel Lock Bit */
#define AT91C_DMA_LOCK_B      (0x1 << 17) /**< (DMA) Bus Lock Bit */
#define AT91C_DMA_DS_HS_POL   (0x1 << 18) /**< (DMA) Destination Handshaking Interface Polarity */
#define AT91C_DMA_SR_HS_POL   (0x1 << 19) /**< (DMA) Source Handshaking Interface Polarity */
#define AT91C_DMA_MAX_ABRST   (0x3FF << 20) /**< (DMA) Maximum AMBA Burst Length */
#define AT91C_DMA_RELOAD_SR   (0x1 << 30) /**< (DMA) Automatic Source Reload */
#define AT91C_DMA_RELOAD_DS   (0x1 << 31) /**< (DMA) Automatic Destination Reload */
/* --- Register DMA_CFGh */
#define AT91C_DMA_FCMODE      (0x1 << 0 ) /**< (DMA) Flow Control Mode */
#define AT91C_DMA_FIFO_MODE   (0x1 << 1 ) /**< (DMA) Fifo Mode Select */
#define AT91C_DMA_PROTCTL     (0x7 << 2 ) /**< (DMA) Protection Control */
#define AT91C_DMA_DS_UPD_EN   (0x1 << 5 ) /**< (DMA) Destination Status Update Enable */
#define AT91C_DMA_SS_UPD_EN   (0x1 << 6 ) /**< (DMA) Source Status Update Enable */
#define AT91C_DMA_SRC_PER     (0xF << 7 ) /**< (DMA) Source Hardware Handshaking Interface */
#define AT91C_DMA_DEST_PER    (0xF << 11) /**< (DMA) Destination Hardware Handshaking Interface */
/* --- Register DMA_SGR */
#define AT91C_DMA_SGI         (0xFFFFF << 0 ) /**< (DMA) Source Gather Interval */
#define AT91C_DMA_SGC         (0xFFF << 20) /**< (DMA) Source Gather Count */
/* --- Register DMA_DSR */
#define AT91C_DMA_DSI         (0xFFFFF << 0 ) /**< (DMA) Destination Scatter Interval */
#define AT91C_DMA_DSC         (0xFFF << 20) /**< (DMA) Destination Scatter Count */
/* --- Register DMA_RAWTFR */
#define AT91C_DMA_RAW         (0x7 << 0 ) /**< (DMA) Raw Interrupt for each Channel */
/* --- Register DMA_RAWBLOCK */
#define AT91C_DMA_RAW         (0x7 << 0 ) /**< (DMA) Raw Interrupt for each Channel */
/* --- Register DMA_RAWSRCTRAN */
#define AT91C_DMA_RAW         (0x7 << 0 ) /**< (DMA) Raw Interrupt for each Channel */
/* --- Register DMA_RAWDSTTRAN */
#define AT91C_DMA_RAW         (0x7 << 0 ) /**< (DMA) Raw Interrupt for each Channel */
/* --- Register DMA_RAWERR */
#define AT91C_DMA_RAW         (0x7 << 0 ) /**< (DMA) Raw Interrupt for each Channel */
/* --- Register DMA_STATUSTFR */
#define AT91C_DMA_STATUS      (0x7 << 0 ) /**< (DMA) Interrupt for each Channel */
/* --- Register DMA_STATUSBLOCK */
#define AT91C_DMA_STATUS      (0x7 << 0 ) /**< (DMA) Interrupt for each Channel */
/* --- Register DMA_STATUSSRCTRAN */
#define AT91C_DMA_STATUS      (0x7 << 0 ) /**< (DMA) Interrupt for each Channel */
/* --- Register DMA_STATUSDSTTRAN */
#define AT91C_DMA_STATUS      (0x7 << 0 ) /**< (DMA) Interrupt for each Channel */
/* --- Register DMA_STATUSERR */
#define AT91C_DMA_RAW         (0x7 << 0 ) /**< (DMA) Raw Interrupt for each Channel */
/* --- Register DMA_MASKTFR */
#define AT91C_DMA_INT_MASK    (0x7 << 0 ) /**< (DMA) Interrupt Mask for each Channel */
#define AT91C_DMA_INT_M_WE    (0x7 << 8 ) /**< (DMA) Interrupt Mask Write Enable for each Channel */
/* --- Register DMA_MASKBLOCK */
#define AT91C_DMA_INT_MASK    (0x7 << 0 ) /**< (DMA) Interrupt Mask for each Channel */
#define AT91C_DMA_INT_M_WE    (0x7 << 8 ) /**< (DMA) Interrupt Mask Write Enable for each Channel */
/* --- Register DMA_MASKSRCTRAN */
#define AT91C_DMA_INT_MASK    (0x7 << 0 ) /**< (DMA) Interrupt Mask for each Channel */
#define AT91C_DMA_INT_M_WE    (0x7 << 8 ) /**< (DMA) Interrupt Mask Write Enable for each Channel */
/* --- Register DMA_MASKDSTTRAN */
#define AT91C_DMA_INT_MASK    (0x7 << 0 ) /**< (DMA) Interrupt Mask for each Channel */
#define AT91C_DMA_INT_M_WE    (0x7 << 8 ) /**< (DMA) Interrupt Mask Write Enable for each Channel */
/* --- Register DMA_MASKERR */
#define AT91C_DMA_INT_MASK    (0x7 << 0 ) /**< (DMA) Interrupt Mask for each Channel */
#define AT91C_DMA_INT_M_WE    (0x7 << 8 ) /**< (DMA) Interrupt Mask Write Enable for each Channel */
/* --- Register DMA_CLEARTFR */
#define AT91C_DMA_CLEAR       (0x7 << 0 ) /**< (DMA) Interrupt Clear for each Channel */
/* --- Register DMA_CLEARBLOCK */
#define AT91C_DMA_CLEAR       (0x7 << 0 ) /**< (DMA) Interrupt Clear for each Channel */
/* --- Register DMA_CLEARSRCTRAN */
#define AT91C_DMA_CLEAR       (0x7 << 0 ) /**< (DMA) Interrupt Clear for each Channel */
/* --- Register DMA_CLEARDSTTRAN */
#define AT91C_DMA_CLEAR       (0x7 << 0 ) /**< (DMA) Interrupt Clear for each Channel */
/* --- Register DMA_CLEARERR */
#define AT91C_DMA_CLEAR       (0x7 << 0 ) /**< (DMA) Interrupt Clear for each Channel */
/* --- Register DMA_STATUSINT */
#define AT91C_DMA_TFR         (0x1 << 0 ) /**< (DMA) OR of the content of StatusTfr Register */
#define AT91C_DMA_BLOCK       (0x1 << 1 ) /**< (DMA) OR of the content of StatusBlock Register */
#define AT91C_DMA_SRCT        (0x1 << 2 ) /**< (DMA) OR of the content of StatusSrcTran Register */
#define AT91C_DMA_DSTT        (0x1 << 3 ) /**< (DMA) OR of the content of StatusDstTran Register */
#define AT91C_DMA_ERR         (0x1 << 4 ) /**< (DMA) OR of the content of StatusErr Register */
/* --- Register DMA_REQSRCREG */
#define AT91C_DMA_SRC_REQ     (0x7 << 0 ) /**< (DMA) Source Request */
#define AT91C_DMA_REQ_WE      (0x7 << 8 ) /**< (DMA) Request Write Enable */
/* --- Register DMA_REQDSTREG */
#define AT91C_DMA_DST_REQ     (0x7 << 0 ) /**< (DMA) Destination Request */
#define AT91C_DMA_REQ_WE      (0x7 << 8 ) /**< (DMA) Request Write Enable */
/* --- Register DMA_SGLREQSRCREG */
#define AT91C_DMA_S_SG_REQ    (0x7 << 0 ) /**< (DMA) Source Single Request */
#define AT91C_DMA_REQ_WE      (0x7 << 8 ) /**< (DMA) Request Write Enable */
/* --- Register DMA_SGLREQDSTREG */
#define AT91C_DMA_D_SG_REQ    (0x7 << 0 ) /**< (DMA) Destination Single Request */
#define AT91C_DMA_REQ_WE      (0x7 << 8 ) /**< (DMA) Request Write Enable */
/* --- Register DMA_LSTREQSRCREG */
#define AT91C_DMA_LSTSRC      (0x7 << 0 ) /**< (DMA) Source Last Transaction Request */
#define AT91C_DMA_LSTSR_WE    (0x7 << 8 ) /**< (DMA) Source Last Transaction Request Write Enable */
/* --- Register DMA_LSTREQDSTREG */
#define AT91C_DMA_LSTDST      (0x7 << 0 ) /**< (DMA) Destination Last Transaction Request */
#define AT91C_DMA_LSTDS_WE    (0x7 << 8 ) /**< (DMA) Destination Last Transaction Request Write Enable */
/* --- Register DMA_DMACFGREG */
#define AT91C_DMA_DMA_EN      (0x7 << 0 ) /**< (DMA) Controller Enable */
/* --- Register DMA_CHENREG */
#define AT91C_DMA_CH_EN       (0x7 << 0 ) /**< (DMA) Channel Enable */
#define AT91C_DMA_CH_EN_WE    (0x7 << 8 ) /**< (DMA) Channel Enable Write Enable */
/* --- Register DMA_DMATESTREG */
#define AT91C_DMA_TEST_SLV_IF (0x1 << 0 ) /**< (DMA) Test Mode for Slave Interface */

#endif /* __AT91SAM9263_DMA_H */