at91sam9263_dma.h

最新版IAR FOR ARM（EWARM）5.11中的代码例子

/* linux/include/asm-arm/arch-at91sam9263/at91sam9263_dma.h
 * 
 * Hardware definition for the dma peripheral in the ATMEL at91sam9263 processor
 * 
 * Generated  12/07/2006 (13:13:45) AT91 SW Application Group from DMA_XXXX V1.6
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */


#ifndef __AT91SAM9263_DMA_H
#define __AT91SAM9263_DMA_H

/* -------------------------------------------------------- */
/* DMA ID definitions for  AT91SAM9263           */
/* -------------------------------------------------------- */
#ifndef AT91C_ID_DMA
#define AT91C_ID_DMA   	27 /**< DMA Controller id */
#endif /* AT91C_ID_DMA */

/* -------------------------------------------------------- */
/* DMA Base Address definitions for  AT91SAM9263   */
/* -------------------------------------------------------- */
#define AT91C_BASE_DMA       	0x00800000 /**< DMA base address */

/* -------------------------------------------------------- */
/* PIO definition for DMA hardware peripheral */
/* -------------------------------------------------------- */
#define AT91C_PA31_DMARQ0   	(1 << 31) /**<  */
#define AT91C_PB6_DMARQ1   	(1 << 6) /**<  */
#define AT91C_PD4_DMARQ2   	(1 << 4) /**<  */
#define AT91C_PB24_DMARQ3   	(1 << 24) /**<  */


/* -------------------------------------------------------- */
/* Register offset definition for DMA hardware peripheral */
/* -------------------------------------------------------- */
#define DMA_SAR0 	(0x0000) 	/**< Source Address Register for channel 0 */
#define DMA_DAR0 	(0x0008) 	/**< Destination Address Register for channel 0 */
#define DMA_LLP0 	(0x0010) 	/**< Linked List Pointer Register for channel 0 */
#define DMA_CTL0l 	(0x0018) 	/**< Control Register for channel 0 - low */
#define DMA_CTL0h 	(0x001C) 	/**< Control Register for channel 0 - high */
#define DMA_SSTAT0 	(0x0020) 	/**< Source Status Register for channel 0 */
#define DMA_DSTAT0 	(0x0028) 	/**< Destination Status Register for channel 0 */
#define DMA_SSTATAR0 	(0x0030) 	/**< Source Status Adress Register for channel 0 */
#define DMA_DSTATAR0 	(0x0038) 	/**< Destination Status Adress Register for channel 0 */
#define DMA_CFG0l 	(0x0040) 	/**< Configuration Register for channel 0 - low */
#define DMA_CFG0h 	(0x0044) 	/**< Configuration Register for channel 0 - high */
#define DMA_SGR0 	(0x0048) 	/**< Source Gather Register for channel 0 */
#define DMA_DSR0 	(0x0050) 	/**< Destination Scatter Register for channel 0 */
#define DMA_SAR1 	(0x0058) 	/**< Source Address Register for channel 1 */
#define DMA_DAR1 	(0x0060) 	/**< Destination Address Register for channel 1 */
#define DMA_LLP1 	(0x0068) 	/**< Linked List Pointer Register for channel 1 */
#define DMA_CTL1l 	(0x0070) 	/**< Control Register for channel 1 - low */
#define DMA_CTL1h 	(0x0074) 	/**< Control Register for channel 1 - high */
#define DMA_SSTAT1 	(0x0078) 	/**< Source Status Register for channel 1 */
#define DMA_DSTAT1 	(0x0080) 	/**< Destination Status Register for channel 1 */
#define DMA_SSTATAR1 	(0x0088) 	/**< Source Status Adress Register for channel 1 */
#define DMA_DSTATAR1 	(0x0090) 	/**< Destination Status Adress Register for channel 1 */
#define DMA_CFG1l 	(0x0098) 	/**< Configuration Register for channel 1 - low */
#define DMA_CFG1h 	(0x009C) 	/**< Configuration Register for channel 1 - high */
#define DMA_SGR1 	(0x00A0) 	/**< Source Gather Register for channel 1 */
#define DMA_DSR1 	(0x00A8) 	/**< Destination Scatter Register for channel 1 */
#define DMA_RAWTFR 	(0x02C0) 	/**< Raw Status for IntTfr Interrupt */
#define DMA_RAWBLOCK 	(0x02C8) 	/**< Raw Status for IntBlock Interrupt */
#define DMA_RAWSRCTRAN 	(0x02D0) 	/**< Raw Status for IntSrcTran Interrupt */
#define DMA_RAWDSTTRAN 	(0x02D8) 	/**< Raw Status for IntDstTran Interrupt */
#define DMA_RAWERR 	(0x02E0) 	/**< Raw Status for IntErr Interrupt */
#define DMA_STATUSTFR 	(0x02E8) 	/**< Status for IntTfr Interrupt */
#define DMA_STATUSBLOCK 	(0x02F0) 	/**< Status for IntBlock Interrupt */
#define DMA_STATUSSRCTRAN 	(0x02F8) 	/**< Status for IntSrcTran Interrupt */
#define DMA_STATUSDSTTRAN 	(0x0300) 	/**< Status for IntDstTran IInterrupt */
#define DMA_STATUSERR 	(0x0308) 	/**< Status for IntErr IInterrupt */
#define DMA_MASKTFR 	(0x0310) 	/**< Mask for IntTfr Interrupt */
#define DMA_MASKBLOCK 	(0x0318) 	/**< Mask for IntBlock Interrupt */
#define DMA_MASKSRCTRAN 	(0x0320) 	/**< Mask for IntSrcTran Interrupt */
#define DMA_MASKDSTTRAN 	(0x0328) 	/**< Mask for IntDstTran Interrupt */
#define DMA_MASKERR 	(0x0330) 	/**< Mask for IntErr Interrupt */
#define DMA_CLEARTFR 	(0x0338) 	/**< Clear for IntTfr Interrupt */
#define DMA_CLEARBLOCK 	(0x0340) 	/**< Clear for IntBlock Interrupt */
#define DMA_CLEARSRCTRAN 	(0x0348) 	/**< Clear for IntSrcTran Interrupt */
#define DMA_CLEARDSTTRAN 	(0x0350) 	/**< Clear for IntDstTran IInterrupt */
#define DMA_CLEARERR 	(0x0358) 	/**< Clear for IntErr Interrupt */
#define DMA_STATUSINT 	(0x0360) 	/**< Status for each Interrupt Type */
#define DMA_REQSRCREG 	(0x0368) 	/**< Source Software Transaction Request Register */
#define DMA_REQDSTREG 	(0x0370) 	/**< Destination Software Transaction Request Register */
#define DMA_SGLREQSRCREG 	(0x0378) 	/**< Single Source Software Transaction Request Register */
#define DMA_SGLREQDSTREG 	(0x0380) 	/**< Single Destination Software Transaction Request Register */
#define DMA_LSTREQSRCREG 	(0x0388) 	/**< Last Source Software Transaction Request Register */
#define DMA_LSTREQDSTREG 	(0x0390) 	/**< Last Destination Software Transaction Request Register */
#define DMA_DMACFGREG 	(0x0398) 	/**< DW_ahb_dmac Configuration Register */
#define DMA_CHENREG 	(0x03A0) 	/**< DW_ahb_dmac Channel Enable Register */
#define DMA_DMAIDREG 	(0x03A8) 	/**< DW_ahb_dmac ID Register */
#define DMA_DMATESTREG 	(0x03B0) 	/**< DW_ahb_dmac Test Register */
#define DMA_VERSIONID 	(0x03B8) 	/**< DW_ahb_dmac Version ID Register */

/* -------------------------------------------------------- */
/* Bitfields definition for DMA hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register DMA_SAR */
#define AT91C_DMA_SADD        (0x0 << 0 ) /**< (DMA) Source Address of DMA Transfer */
/* --- Register DMA_DAR */
#define AT91C_DMA_DADD        (0x0 << 0 ) /**< (DMA) Destination Address of DMA Transfer */
/* --- Register DMA_LLP */
#define AT91C_DMA_LOC         (0x0 << 0 ) /**< (DMA) Address of the Next LLI */
/* --- Register DMA_CTLl */
#define AT91C_DMA_INT_EN      (0x1 << 0 ) /**< (DMA) Interrupt Enable Bit */
#define AT91C_DMA_DST_TR_WIDTH (0x7 << 1 ) /**< (DMA) Destination Transfer Width */
#define AT91C_DMA_SRC_TR_WIDTH (0x7 << 4 ) /**< (DMA) Source Transfer Width */
#define AT91C_DMA_DINC        (0x3 << 7 ) /**< (DMA) Destination Address Increment */
#define AT91C_DMA_SINC        (0x3 << 9 ) /**< (DMA) Source Address Increment */
#define AT91C_DMA_DEST_MSIZE  (0x7 << 11) /**< (DMA) Destination Burst Transaction Length */
#define AT91C_DMA_SRC_MSIZE   (0x7 << 14) /**< (DMA) Source Burst Transaction Length */
#define AT91C_DMA_S_GATH_EN   (0x1 << 17) /**< (DMA) Source Gather Enable Bit */
#define AT91C_DMA_D_SCAT_EN   (0x1 << 18) /**< (DMA) Destination Scatter Enable Bit */
#define AT91C_DMA_TT_FC       (0x7 << 20) /**< (DMA) Transfer Type and Flow Control */
#define AT91C_DMA_DMS         (0x3 << 23) /**< (DMA) Destination Master Select */
#define AT91C_DMA_SMS         (0x3 << 25) /**< (DMA) Source Master Select */
#define AT91C_DMA_LLP_D_EN    (0x1 << 27) /**< (DMA) Destination Block Chaining Enable */
#define AT91C_DMA_LLP_S_EN    (0x1 << 28) /**< (DMA) Source Block Chaining Enable */
/* --- Register DMA_CTLh */
#define AT91C_DMA_BLOCK_TS    (0xFFF << 0 ) /**< (DMA) Block Transfer Size */
#define AT91C_DMA_DONE        (0x1 << 12) /**< (DMA) Done bit */
/* --- Register DMA_CFGl */
#define AT91C_DMA_CH_PRIOR    (0x7 << 5 ) /**< (DMA) Channel Priority */
#define AT91C_DMA_CH_SUSP     (0x1 << 8 ) /**< (DMA) Channel Suspend */
#define AT91C_DMA_FIFO_EMPT   (0x1 << 9 ) /**< (DMA) Fifo Empty */
#define AT91C_DMA_HS_SEL_DS   (0x1 << 10) /**< (DMA) Destination Software or Hardware Handshaking Select */
#define AT91C_DMA_HS_SEL_SR   (0x1 << 11) /**< (DMA) Source Software or Hardware Handshaking Select */
#define AT91C_DMA_LOCK_CH_L   (0x3 << 12) /**< (DMA) Channel Lock Level */
#define AT91C_DMA_LOCK_B_L    (0x3 << 14) /**< (DMA) Bus Lock Level */
#define AT91C_DMA_LOCK_CH     (0x1 << 16) /**< (DMA) Channel Lock Bit */
#define AT91C_DMA_LOCK_B      (0x1 << 17) /**< (DMA) Bus Lock Bit */