at91sam9263_mci.h

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/* linux/include/asm-arm/arch-at91sam9263/at91sam9263_mci.h
 * 
 * Hardware definition for the mci peripheral in the ATMEL at91sam9263 processor
 * 
 * Generated  12/07/2006 (13:13:46) AT91 SW Application Group from MCI_6101E V1.1
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */


#ifndef __AT91SAM9263_MCI_H
#define __AT91SAM9263_MCI_H

/* -------------------------------------------------------- */
/* MCI ID definitions for  AT91SAM9263           */
/* -------------------------------------------------------- */
#ifndef AT91C_ID_MCI0
#define AT91C_ID_MCI0  	10 /**< Multimedia Card Interface 0 id */
#endif /* AT91C_ID_MCI0 */
#ifndef AT91C_ID_MCI1
#define AT91C_ID_MCI1  	11 /**< Multimedia Card Interface 1 id */
#endif /* AT91C_ID_MCI1 */

/* -------------------------------------------------------- */
/* MCI Base Address definitions for  AT91SAM9263   */
/* -------------------------------------------------------- */
#define AT91C_BASE_MCI0      	0xFFF80000 /**< MCI0 base address */
#define AT91C_BASE_MCI1      	0xFFF84000 /**< MCI1 base address */

/* -------------------------------------------------------- */
/* PIO definition for MCI hardware peripheral */
/* -------------------------------------------------------- */
#define AT91C_PA1_MCI0_CDA 	(1 << 1) /**<  */
#define AT91C_PA16_MCI0_CDB 	(1 << 16) /**<  */
#define AT91C_PA12_MCI0_CK  	(1 << 12) /**<  */
#define AT91C_PA0_MCI0_DA0 	(1 << 0) /**<  */
#define AT91C_PA3_MCI0_DA1 	(1 << 3) /**<  */
#define AT91C_PA4_MCI0_DA2 	(1 << 4) /**<  */
#define AT91C_PA5_MCI0_DA3 	(1 << 5) /**<  */
#define AT91C_PA17_MCI0_DB0 	(1 << 17) /**<  */
#define AT91C_PA18_MCI0_DB1 	(1 << 18) /**<  */
#define AT91C_PA19_MCI0_DB2 	(1 << 19) /**<  */
#define AT91C_PA20_MCI0_DB3 	(1 << 20) /**<  */

#define AT91C_PA7_MCI1_CDA 	(1 << 7) /**<  */
#define AT91C_PA21_MCI1_CDB 	(1 << 21) /**<  */
#define AT91C_PA6_MCI1_CK  	(1 << 6) /**<  */
#define AT91C_PA8_MCI1_DA0 	(1 << 8) /**<  */
#define AT91C_PA9_MCI1_DA1 	(1 << 9) /**<  */
#define AT91C_PA10_MCI1_DA2 	(1 << 10) /**<  */
#define AT91C_PA11_MCI1_DA3 	(1 << 11) /**<  */
#define AT91C_PA22_MCI1_DB0 	(1 << 22) /**<  */
#define AT91C_PA23_MCI1_DB1 	(1 << 23) /**<  */
#define AT91C_PA24_MCI1_DB2 	(1 << 24) /**<  */
#define AT91C_PA25_MCI1_DB3 	(1 << 25) /**<  */


/* -------------------------------------------------------- */
/* Register offset definition for MCI hardware peripheral */
/* -------------------------------------------------------- */
#define MCI_CR 	(0x0000) 	/**< MCI Control Register */
#define MCI_MR 	(0x0004) 	/**< MCI Mode Register */
#define MCI_DTOR 	(0x0008) 	/**< MCI Data Timeout Register */
#define MCI_SDCR 	(0x000C) 	/**< MCI SD Card Register */
#define MCI_ARGR 	(0x0010) 	/**< MCI Argument Register */
#define MCI_CMDR 	(0x0014) 	/**< MCI Command Register */
#define MCI_BLKR 	(0x0018) 	/**< MCI Block Register */
#define MCI_RSPR 	(0x0020) 	/**< MCI Response Register */
#define MCI_RDR 	(0x0030) 	/**< MCI Receive Data Register */
#define MCI_TDR 	(0x0034) 	/**< MCI Transmit Data Register */
#define MCI_SR 	(0x0040) 	/**< MCI Status Register */
#define MCI_IER 	(0x0044) 	/**< MCI Interrupt Enable Register */
#define MCI_IDR 	(0x0048) 	/**< MCI Interrupt Disable Register */
#define MCI_IMR 	(0x004C) 	/**< MCI Interrupt Mask Register */
#define MCI_VR 	(0x00FC) 	/**< MCI Version Register */
#define MCI_RPR 	(0x0100) 	/**< Receive Pointer Register */
#define MCI_RCR 	(0x0104) 	/**< Receive Counter Register */
#define MCI_TPR 	(0x0108) 	/**< Transmit Pointer Register */
#define MCI_TCR 	(0x010C) 	/**< Transmit Counter Register */
#define MCI_RNPR 	(0x0110) 	/**< Receive Next Pointer Register */
#define MCI_RNCR 	(0x0114) 	/**< Receive Next Counter Register */
#define MCI_TNPR 	(0x0118) 	/**< Transmit Next Pointer Register */
#define MCI_TNCR 	(0x011C) 	/**< Transmit Next Counter Register */
#define MCI_PTCR 	(0x0120) 	/**< PDC Transfer Control Register */
#define MCI_PTSR 	(0x0124) 	/**< PDC Transfer Status Register */

/* -------------------------------------------------------- */
/* Bitfields definition for MCI hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register MCI_CR */
#define AT91C_MCI_MCIEN       (0x1 << 0 ) /**< (MCI) Multimedia Interface Enable */
#define AT91C_MCI_MCIDIS      (0x1 << 1 ) /**< (MCI) Multimedia Interface Disable */
#define AT91C_MCI_PWSEN       (0x1 << 2 ) /**< (MCI) Power Save Mode Enable */
#define AT91C_MCI_PWSDIS      (0x1 << 3 ) /**< (MCI) Power Save Mode Disable */
#define AT91C_MCI_SWRST       (0x1 << 7 ) /**< (MCI) MCI Software reset */
/* --- Register MCI_MR */
#define AT91C_MCI_CLKDIV      (0xFF << 0 ) /**< (MCI) Clock Divider */
#define AT91C_MCI_PWSDIV      (0x7 << 8 ) /**< (MCI) Power Saving Divider */
#define AT91C_MCI_RDPROOF     (0x1 << 11) /**< (MCI) Read Proof Enable */
#define AT91C_MCI_WRPROOF     (0x1 << 12) /**< (MCI) Write Proof Enable */
#define AT91C_MCI_PDCFBYTE    (0x1 << 13) /**< (MCI) PDC Force Byte Transfer */
#define AT91C_MCI_PDCPADV     (0x1 << 14) /**< (MCI) PDC Padding Value */
#define AT91C_MCI_PDCMODE     (0x1 << 15) /**< (MCI) PDC Oriented Mode */
#define AT91C_MCI_BLKLEN      (0xFFFF << 16) /**< (MCI) Data Block Length */
/* --- Register MCI_DTOR */
#define AT91C_MCI_DTOCYC      (0xF << 0 ) /**< (MCI) Data Timeout Cycle Number */
#define AT91C_MCI_DTOMUL      (0x7 << 4 ) /**< (MCI) Data Timeout Multiplier */
#define 	AT91C_MCI_DTOMUL_1                    (0x0 <<  4) /**< (MCI) DTOCYC x 1 */
#define 	AT91C_MCI_DTOMUL_16                   (0x1 <<  4) /**< (MCI) DTOCYC x 16 */
#define 	AT91C_MCI_DTOMUL_128                  (0x2 <<  4) /**< (MCI) DTOCYC x 128 */
#define 	AT91C_MCI_DTOMUL_256                  (0x3 <<  4) /**< (MCI) DTOCYC x 256 */
#define 	AT91C_MCI_DTOMUL_1024                 (0x4 <<  4) /**< (MCI) DTOCYC x 1024 */
#define 	AT91C_MCI_DTOMUL_4096                 (0x5 <<  4) /**< (MCI) DTOCYC x 4096 */
#define 	AT91C_MCI_DTOMUL_65536                (0x6 <<  4) /**< (MCI) DTOCYC x 65536 */
#define 	AT91C_MCI_DTOMUL_1048576              (0x7 <<  4) /**< (MCI) DTOCYC x 1048576 */
/* --- Register MCI_SDCR */