at91sam9263_inc.h
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// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ----------------------------------------------------------------------------
// File Name : AT91SAM9263.h
// Object : AT91SAM9263 definitions
// Generated : AT91 SW Application Group 12/07/2006 (13:13:32)
//
// CVS Reference : /AT91SAM9263.pl/1.2/Fri Nov 10 12:56:00 2006//
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// CVS Reference : /PMC_SAM9262.pl/1.4/Mon Mar 7 18:03:13 2005//
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// ----------------------------------------------------------------------------
// Hardware register definition
// *****************************************************************************
// SOFTWARE API DEFINITION FOR System Peripherals
// *****************************************************************************
// -------- GPBR : (SYS Offset: 0x1d60) GPBR General Purpose Register --------
#define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value
// *****************************************************************************
// SOFTWARE API DEFINITION FOR External Bus Interface 0
// *****************************************************************************
// *** Register offset in AT91S_EBI0 structure ***
#define EBI0_DUMMY ( 0) // Dummy register - Do not use
// *****************************************************************************
// SOFTWARE API DEFINITION FOR SDRAM Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_SDRAMC structure ***
#define SDRAMC_MR ( 0) // SDRAM Controller Mode Register
#define SDRAMC_TR ( 4) // SDRAM Controller Refresh Timer Register
#define SDRAMC_CR ( 8) // SDRAM Controller Configuration Register
#define SDRAMC_HSR (12) // SDRAM Controller High Speed Register
#define SDRAMC_LPR (16) // SDRAM Controller Low Power Register
#define SDRAMC_IER (20) // SDRAM Controller Interrupt Enable Register
#define SDRAMC_IDR (24) // SDRAM Controller Interrupt Disable Register
#define SDRAMC_IMR (28) // SDRAM Controller Interrupt Mask Register
#define SDRAMC_ISR (32) // SDRAM Controller Interrupt Mask Register
#define SDRAMC_MDR (36) // SDRAM Memory Device Register
// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register --------
#define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode
#define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode
#define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access
#define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
#define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access
#define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh
#define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register
#define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode
// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register --------
#define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter
// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register --------
#define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits
#define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits
#define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits
#define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits
#define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits
#define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits
#define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits
#define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits
#define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits
#define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks
#define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks
#define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks
#define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency
#define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles
#define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles
#define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width
#define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus
#define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus
#define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles
#define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles
#define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles
#define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0
#define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1
#define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2
#define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3
#define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4
#define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5
#define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6
#define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7
#define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8
#define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9
#define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10
#define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11
#define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12
#define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13
#define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14
#define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15
#define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles
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