at91sam9263.rdf

来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· RDF 代码 · 共 1,539 行 · 第 1/5 页

AT91C_MATRIX_PRAS6.name="AT91C_MATRIX_PRAS6"
AT91C_MATRIX_PRAS6.description=" PRAS6"
AT91C_MATRIX_PRAS6.helpkey=" PRAS6"
AT91C_MATRIX_PRAS6.access=memorymapped
AT91C_MATRIX_PRAS6.address=0xFFFFECB0
AT91C_MATRIX_PRAS6.width=32
AT91C_MATRIX_PRAS6.byteEndian=little
AT91C_MATRIX_SCFG2.name="AT91C_MATRIX_SCFG2"
AT91C_MATRIX_SCFG2.description=" Slave Configuration Register 2"
AT91C_MATRIX_SCFG2.helpkey=" Slave Configuration Register 2"
AT91C_MATRIX_SCFG2.access=memorymapped
AT91C_MATRIX_SCFG2.address=0xFFFFEC48
AT91C_MATRIX_SCFG2.width=32
AT91C_MATRIX_SCFG2.byteEndian=little
AT91C_MATRIX_PRBS3.name="AT91C_MATRIX_PRBS3"
AT91C_MATRIX_PRBS3.description=" PRBS3"
AT91C_MATRIX_PRBS3.helpkey=" PRBS3"
AT91C_MATRIX_PRBS3.access=memorymapped
AT91C_MATRIX_PRBS3.address=0xFFFFEC9C
AT91C_MATRIX_PRBS3.width=32
AT91C_MATRIX_PRBS3.byteEndian=little
# ========== Register definition for CCFG peripheral ========== 
AT91C_CCFG_MATRIXVERSION.name="AT91C_CCFG_MATRIXVERSION"
AT91C_CCFG_MATRIXVERSION.description=" Version Register"
AT91C_CCFG_MATRIXVERSION.helpkey=" Version Register"
AT91C_CCFG_MATRIXVERSION.access=memorymapped
AT91C_CCFG_MATRIXVERSION.address=0xFFFFEDFC
AT91C_CCFG_MATRIXVERSION.width=32
AT91C_CCFG_MATRIXVERSION.byteEndian=little
AT91C_CCFG_MATRIXVERSION.permission.write=none
AT91C_CCFG_TCMR.name="AT91C_CCFG_TCMR"
AT91C_CCFG_TCMR.description=" TCM configuration"
AT91C_CCFG_TCMR.helpkey=" TCM configuration"
AT91C_CCFG_TCMR.access=memorymapped
AT91C_CCFG_TCMR.address=0xFFFFED14
AT91C_CCFG_TCMR.width=32
AT91C_CCFG_TCMR.byteEndian=little
AT91C_CCFG_EBI0CSA.name="AT91C_CCFG_EBI0CSA"
AT91C_CCFG_EBI0CSA.description=" EBI0 Chip Select Assignement Register"
AT91C_CCFG_EBI0CSA.helpkey=" EBI0 Chip Select Assignement Register"
AT91C_CCFG_EBI0CSA.access=memorymapped
AT91C_CCFG_EBI0CSA.address=0xFFFFED20
AT91C_CCFG_EBI0CSA.width=32
AT91C_CCFG_EBI0CSA.byteEndian=little
AT91C_CCFG_EBI1CSA.name="AT91C_CCFG_EBI1CSA"
AT91C_CCFG_EBI1CSA.description=" EBI1 Chip Select Assignement Register"
AT91C_CCFG_EBI1CSA.helpkey=" EBI1 Chip Select Assignement Register"
AT91C_CCFG_EBI1CSA.access=memorymapped
AT91C_CCFG_EBI1CSA.address=0xFFFFED24
AT91C_CCFG_EBI1CSA.width=32
AT91C_CCFG_EBI1CSA.byteEndian=little
# ========== Register definition for PDC_DBGU peripheral ========== 
AT91C_DBGU_PTCR.name="AT91C_DBGU_PTCR"
AT91C_DBGU_PTCR.description="PDC Transfer Control Register"
AT91C_DBGU_PTCR.helpkey="PDC Transfer Control Register"
AT91C_DBGU_PTCR.access=memorymapped
AT91C_DBGU_PTCR.address=0xFFFFEF20
AT91C_DBGU_PTCR.width=32
AT91C_DBGU_PTCR.byteEndian=little
AT91C_DBGU_PTCR.type=enum
AT91C_DBGU_PTCR.enum.0.name=*** Write only ***
AT91C_DBGU_PTCR.enum.1.name=Error
AT91C_DBGU_RCR.name="AT91C_DBGU_RCR"
AT91C_DBGU_RCR.description="Receive Counter Register"
AT91C_DBGU_RCR.helpkey="Receive Counter Register"
AT91C_DBGU_RCR.access=memorymapped
AT91C_DBGU_RCR.address=0xFFFFEF04
AT91C_DBGU_RCR.width=32
AT91C_DBGU_RCR.byteEndian=little
AT91C_DBGU_TCR.name="AT91C_DBGU_TCR"
AT91C_DBGU_TCR.description="Transmit Counter Register"
AT91C_DBGU_TCR.helpkey="Transmit Counter Register"
AT91C_DBGU_TCR.access=memorymapped
AT91C_DBGU_TCR.address=0xFFFFEF0C
AT91C_DBGU_TCR.width=32
AT91C_DBGU_TCR.byteEndian=little
AT91C_DBGU_RNCR.name="AT91C_DBGU_RNCR"
AT91C_DBGU_RNCR.description="Receive Next Counter Register"
AT91C_DBGU_RNCR.helpkey="Receive Next Counter Register"
AT91C_DBGU_RNCR.access=memorymapped
AT91C_DBGU_RNCR.address=0xFFFFEF14
AT91C_DBGU_RNCR.width=32
AT91C_DBGU_RNCR.byteEndian=little
AT91C_DBGU_TNPR.name="AT91C_DBGU_TNPR"
AT91C_DBGU_TNPR.description="Transmit Next Pointer Register"
AT91C_DBGU_TNPR.helpkey="Transmit Next Pointer Register"
AT91C_DBGU_TNPR.access=memorymapped
AT91C_DBGU_TNPR.address=0xFFFFEF18
AT91C_DBGU_TNPR.width=32
AT91C_DBGU_TNPR.byteEndian=little
AT91C_DBGU_RNPR.name="AT91C_DBGU_RNPR"
AT91C_DBGU_RNPR.description="Receive Next Pointer Register"
AT91C_DBGU_RNPR.helpkey="Receive Next Pointer Register"
AT91C_DBGU_RNPR.access=memorymapped
AT91C_DBGU_RNPR.address=0xFFFFEF10
AT91C_DBGU_RNPR.width=32
AT91C_DBGU_RNPR.byteEndian=little
AT91C_DBGU_PTSR.name="AT91C_DBGU_PTSR"
AT91C_DBGU_PTSR.description="PDC Transfer Status Register"
AT91C_DBGU_PTSR.helpkey="PDC Transfer Status Register"
AT91C_DBGU_PTSR.access=memorymapped
AT91C_DBGU_PTSR.address=0xFFFFEF24
AT91C_DBGU_PTSR.width=32
AT91C_DBGU_PTSR.byteEndian=little
AT91C_DBGU_PTSR.permission.write=none
AT91C_DBGU_RPR.name="AT91C_DBGU_RPR"
AT91C_DBGU_RPR.description="Receive Pointer Register"
AT91C_DBGU_RPR.helpkey="Receive Pointer Register"
AT91C_DBGU_RPR.access=memorymapped
AT91C_DBGU_RPR.address=0xFFFFEF00
AT91C_DBGU_RPR.width=32
AT91C_DBGU_RPR.byteEndian=little
AT91C_DBGU_TPR.name="AT91C_DBGU_TPR"
AT91C_DBGU_TPR.description="Transmit Pointer Register"
AT91C_DBGU_TPR.helpkey="Transmit Pointer Register"
AT91C_DBGU_TPR.access=memorymapped
AT91C_DBGU_TPR.address=0xFFFFEF08
AT91C_DBGU_TPR.width=32
AT91C_DBGU_TPR.byteEndian=little
AT91C_DBGU_TNCR.name="AT91C_DBGU_TNCR"
AT91C_DBGU_TNCR.description="Transmit Next Counter Register"
AT91C_DBGU_TNCR.helpkey="Transmit Next Counter Register"
AT91C_DBGU_TNCR.access=memorymapped
AT91C_DBGU_TNCR.address=0xFFFFEF1C
AT91C_DBGU_TNCR.width=32
AT91C_DBGU_TNCR.byteEndian=little
# ========== Register definition for DBGU peripheral ========== 
AT91C_DBGU_BRGR.name="AT91C_DBGU_BRGR"
AT91C_DBGU_BRGR.description="Baud Rate Generator Register"
AT91C_DBGU_BRGR.helpkey="Baud Rate Generator Register"
AT91C_DBGU_BRGR.access=memorymapped
AT91C_DBGU_BRGR.address=0xFFFFEE20
AT91C_DBGU_BRGR.width=32
AT91C_DBGU_BRGR.byteEndian=little
AT91C_DBGU_CR.name="AT91C_DBGU_CR"
AT91C_DBGU_CR.description="Control Register"
AT91C_DBGU_CR.helpkey="Control Register"
AT91C_DBGU_CR.access=memorymapped
AT91C_DBGU_CR.address=0xFFFFEE00
AT91C_DBGU_CR.width=32
AT91C_DBGU_CR.byteEndian=little
AT91C_DBGU_CR.type=enum
AT91C_DBGU_CR.enum.0.name=*** Write only ***
AT91C_DBGU_CR.enum.1.name=Error
AT91C_DBGU_THR.name="AT91C_DBGU_THR"
AT91C_DBGU_THR.description="Transmitter Holding Register"
AT91C_DBGU_THR.helpkey="Transmitter Holding Register"
AT91C_DBGU_THR.access=memorymapped
AT91C_DBGU_THR.address=0xFFFFEE1C
AT91C_DBGU_THR.width=32
AT91C_DBGU_THR.byteEndian=little
AT91C_DBGU_THR.type=enum
AT91C_DBGU_THR.enum.0.name=*** Write only ***
AT91C_DBGU_THR.enum.1.name=Error
AT91C_DBGU_IDR.name="AT91C_DBGU_IDR"
AT91C_DBGU_IDR.description="Interrupt Disable Register"
AT91C_DBGU_IDR.helpkey="Interrupt Disable Register"
AT91C_DBGU_IDR.access=memorymapped
AT91C_DBGU_IDR.address=0xFFFFEE0C
AT91C_DBGU_IDR.width=32
AT91C_DBGU_IDR.byteEndian=little
AT91C_DBGU_IDR.type=enum
AT91C_DBGU_IDR.enum.0.name=*** Write only ***
AT91C_DBGU_IDR.enum.1.name=Error
AT91C_DBGU_EXID.name="AT91C_DBGU_EXID"
AT91C_DBGU_EXID.description="Chip ID Extension Register"
AT91C_DBGU_EXID.helpkey="Chip ID Extension Register"
AT91C_DBGU_EXID.access=memorymapped
AT91C_DBGU_EXID.address=0xFFFFEE44
AT91C_DBGU_EXID.width=32
AT91C_DBGU_EXID.byteEndian=little
AT91C_DBGU_EXID.permission.write=none
AT91C_DBGU_IMR.name="AT91C_DBGU_IMR"
AT91C_DBGU_IMR.description="Interrupt Mask Register"
AT91C_DBGU_IMR.helpkey="Interrupt Mask Register"
AT91C_DBGU_IMR.access=memorymapped
AT91C_DBGU_IMR.address=0xFFFFEE10
AT91C_DBGU_IMR.width=32
AT91C_DBGU_IMR.byteEndian=little
AT91C_DBGU_IMR.permission.write=none
AT91C_DBGU_FNTR.name="AT91C_DBGU_FNTR"
AT91C_DBGU_FNTR.description="Force NTRST Register"
AT91C_DBGU_FNTR.helpkey="Force NTRST Register"
AT91C_DBGU_FNTR.access=memorymapped
AT91C_DBGU_FNTR.address=0xFFFFEE48
AT91C_DBGU_FNTR.width=32
AT91C_DBGU_FNTR.byteEndian=little
AT91C_DBGU_IER.name="AT91C_DBGU_IER"
AT91C_DBGU_IER.description="Interrupt Enable Register"
AT91C_DBGU_IER.helpkey="Interrupt Enable Register"
AT91C_DBGU_IER.access=memorymapped
AT91C_DBGU_IER.address=0xFFFFEE08
AT91C_DBGU_IER.width=32
AT91C_DBGU_IER.byteEndian=little
AT91C_DBGU_IER.type=enum
AT91C_DBGU_IER.enum.0.name=*** Write only ***
AT91C_DBGU_IER.enum.1.name=Error
AT91C_DBGU_CSR.name="AT91C_DBGU_CSR"
AT91C_DBGU_CSR.description="Channel Status Register"
AT91C_DBGU_CSR.helpkey="Channel Status Register"
AT91C_DBGU_CSR.access=memorymapped
AT91C_DBGU_CSR.address=0xFFFFEE14
AT91C_DBGU_CSR.width=32
AT91C_DBGU_CSR.byteEndian=little
AT91C_DBGU_CSR.permission.write=none
AT91C_DBGU_MR.name="AT91C_DBGU_MR"
AT91C_DBGU_MR.description="Mode Register"
AT91C_DBGU_MR.helpkey="Mode Register"
AT91C_DBGU_MR.access=memorymapped
AT91C_DBGU_MR.address=0xFFFFEE04
AT91C_DBGU_MR.width=32
AT91C_DBGU_MR.byteEndian=little
AT91C_DBGU_RHR.name="AT91C_DBGU_RHR"
AT91C_DBGU_RHR.description="Receiver Holding Register"
AT91C_DBGU_RHR.helpkey="Receiver Holding Register"
AT91C_DBGU_RHR.access=memorymapped
AT91C_DBGU_RHR.address=0xFFFFEE18
AT91C_DBGU_RHR.width=32
AT91C_DBGU_RHR.byteEndian=little
AT91C_DBGU_RHR.permission.write=none
AT91C_DBGU_CIDR.name="AT91C_DBGU_CIDR"
AT91C_DBGU_CIDR.description="Chip ID Register"
AT91C_DBGU_CIDR.helpkey="Chip ID Register"
AT91C_DBGU_CIDR.access=memorymapped
AT91C_DBGU_CIDR.address=0xFFFFEE40
AT91C_DBGU_CIDR.width=32
AT91C_DBGU_CIDR.byteEndian=little
AT91C_DBGU_CIDR.permission.write=none
# ========== Register definition for AIC peripheral ========== 
AT91C_AIC_IVR.name="AT91C_AIC_IVR"
AT91C_AIC_IVR.description="IRQ Vector Register"
AT91C_AIC_IVR.helpkey="IRQ Vector Register"
AT91C_AIC_IVR.access=memorymapped
AT91C_AIC_IVR.address=0xFFFFF100
AT91C_AIC_IVR.width=32
AT91C_AIC_IVR.byteEndian=little
AT91C_AIC_IVR.permission.write=none
AT91C_AIC_SMR.name="AT91C_AIC_SMR"
AT91C_AIC_SMR.description="Source Mode Register"
AT91C_AIC_SMR.helpkey="Source Mode Register"
AT91C_AIC_SMR.access=memorymapped
AT91C_AIC_SMR.address=0xFFFFF000
AT91C_AIC_SMR.width=32
AT91C_AIC_SMR.byteEndian=little
AT91C_AIC_FVR.name="AT91C_AIC_FVR"
AT91C_AIC_FVR.description="FIQ Vector Register"
AT91C_AIC_FVR.helpkey="FIQ Vector Register"
AT91C_AIC_FVR.access=memorymapped
AT91C_AIC_FVR.address=0xFFFFF104
AT91C_AIC_FVR.width=32
AT91C_AIC_FVR.byteEndian=little
AT91C_AIC_FVR.permission.write=none
AT91C_AIC_DCR.name="AT91C_AIC_DCR"
AT91C_AIC_DCR.description="Debug Control Register (Protect)"
AT91C_AIC_DCR.helpkey="Debug Control Register (Protect)"
AT91C_AIC_DCR.access=memorymapped
AT91C_AIC_DCR.address=0xFFFFF138
AT91C_AIC_DCR.width=32
AT91C_AIC_DCR.byteEndian=little
AT91C_AIC_EOICR.name="AT91C_AIC_EOICR"
AT91C_AIC_EOICR.description="End of Interrupt Command Register"
AT91C_AIC_EOICR.helpkey="End of Interrupt Command Register"
AT91C_AIC_EOICR.access=memorymapped
AT91C_AIC_EOICR.address=0xFFFFF130
AT91C_AIC_EOICR.width=32
AT91C_AIC_EOICR.byteEndian=little
AT91C_AIC_EOICR.type=enum
AT91C_AIC_EOICR.enum.0.name=*** Write only ***
AT91C_AIC_EOICR.enum.1.name=Error
AT91C_AIC_SVR.name="AT91C_AIC_SVR"
AT91C_AIC_SVR.description="Source Vector Register"
AT91C_AIC_SVR.helpkey="Source Vector Register"
AT91C_AIC_SVR.access=memorymapped
AT91C_AIC_SVR.address=0xFFFFF080
AT91C_AIC_SVR.width=32
AT91C_AIC_SVR.byteEndian=little
AT91C_AIC_FFSR.name="AT91C_AIC_FFSR"
AT91C_AIC_FFSR.description="Fast Forcing Status Register"
AT91C_AIC_FFSR.helpkey="Fast Forcing Status Register"
AT91C_AIC_FFSR.access=memorymapped
AT91C_AIC_FFSR.address=0xFFFFF148
AT91C_AIC_FFSR.width=32
AT91C_AIC_FFSR.byteEndian=little
AT91C_AIC_FFSR.permission.write=none
AT91C_AIC_ICCR.name="AT91C_AIC_ICCR"
AT91C_AIC_ICCR.description="Interrupt Clear Command Register"
AT91C_AIC_ICCR.helpkey="Interrupt Clear Command Register"
AT91C_AIC_ICCR.access=memorymapped
AT91C_AIC_ICCR.address=0xFFFFF128
AT91C_AIC_ICCR.width=32
AT91C_AIC_ICCR.byteEndian=little
AT91C_AIC_ICCR.type=enum
AT91C_AIC_ICCR.enum.0.name=*** Write only ***
AT91C_AIC_ICCR.enum.1.name=Error
AT91C_AIC_ISR.name="AT91C_AIC_ISR"
AT91C_AIC_ISR.description="Interrupt Status Register"
AT91C_AIC_ISR.helpkey="Interrupt Status Register"
AT91C_AIC_ISR.access=memorymapped
AT91C_AIC_ISR.address=0xFFFFF108
AT91C_AIC_ISR.width=32
AT91C_AIC_ISR.byteEndian=little
AT91C_AIC_ISR.permission.write=none
AT91C_AIC_IMR.name="AT91C_AIC_IMR"
AT91C_AIC_IMR.description="Interrupt Mask Register"
AT91C_AIC_IMR.helpkey="Interrupt Mask Register"
AT91C_AIC_IMR.access=memorymapped
AT91C_AIC_IMR.address=0xFFFFF110
AT91C_AIC_IMR.width=32