dramat91sam9261_ek.mac

来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· MAC 代码 · 共 112 行

setup()
{
  __var hold;
  
  // Disable WDT
  __writeMemory32(0x00008000,0xFFFFFD44,"Memory");  // AT91C_WDTC_WDMR = AT91C_WDTC_WDDIS
  // Init Main OSC
  __writeMemory32(0x00000601,0xFFFFFC20,"Memory");  // AT91C_CKGR_MOR = AT91C_CKGR_MOSCEN | (6 << 8)
  __sleep(10000);  // wait 10ms
  // Init PLLA
  __sleep(10000);  // wait 10ms
  // Configuration for a Quartz 18.432000 MHz
  // PLLA 200.9088 MHz MUL_PLLA = 109UL; DIV_PLLA = 10UL
  // 1MHz   <= PLL Input fequency   <= 32 MHz
  // 80MHz  <= PLL Output fequency  <= 200 MHz (CKGR_PLL is 00)
  // 190MHz <= PLL Output fequency  <= 240 MHz (CKGR_PLL is 10)
  __writeMemory32(0x206C860A,0xFFFFFC28,"Memory");  // AT91C_CKGR_PLLAR = (AT91C_CKGR_SRCA                         |\
                                                    //                     AT91C_CKGR_OUTA_2                       |\
                                                    //                    (AT91C_CKGR_DIVA & ( DIV_PLLA <<  0))    |\
                                                    //                    (AT91C_CKGR_MULA & ((MUL_PLLA-1) << 16)) |\
                                                    //                    (AT91C_CKGR_PLLACOUNT & (6 << 8)))  
  // Wait for PLL stabilization
  __sleep(10000);  // wait 10ms
  // Selection of Master Clock MCLK = PCLK/2
  __writeMemory32(0x00000102,0xFFFFFC30,"Memory");  // AT91C_PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_MDIV_2
  // Wait until the master clock is established
  __sleep(10000);  // wait 10ms  
  // Init SDRAM contrller and memory
  __writeMemory32(0x0001003A,0xFFFFEE30,"Memory");  // AT91C_MATRIX_EBICSA = 0x1003A
  __writeMemory32(0xFFFF0000,0xFFFFF870,"Memory");  // AT91C_PIOC_ASR = AT91C_PC20_D20          |\                                                    
                                                    //                  AT91C_PC21_D21          |\
                                                    //                  AT91C_PC30_D30          |\
                                                    //                  AT91C_PC22_D22          |\
                                                    //                  AT91C_PC31_D31          |\
                                                    //                  AT91C_PC23_D23          |\
                                                    //                  AT91C_PC16_D16          |\
                                                    //                  AT91C_PC24_D24          |\
                                                    //                  AT91C_PC17_D17          |\
                                                    //                  AT91C_PC25_D25          |\
                                                    //                  AT91C_PC18_D18          |\
                                                    //                  AT91C_PC26_D26          |\
                                                    //                  AT91C_PC19_D19          |\
                                                    //                  AT91C_PC27_D27          |\
                                                    //                  AT91C_PC28_D28          |\
                                                    //                  AT91C_PC29_D29)         
  __writeMemory32(0xFFFF0000,0xFFFFF804,"Memory");  // AT91C_PIOC_PDR = AT91C_PC20_D20          |\                                                    
                                                    //                  AT91C_PC21_D21          |\
                                                    //                  AT91C_PC30_D30          |\
                                                    //                  AT91C_PC22_D22          |\
                                                    //                  AT91C_PC31_D31          |\
                                                    //                  AT91C_PC23_D23          |\
                                                    //                  AT91C_PC16_D16          |\
                                                    //                  AT91C_PC24_D24          |\
                                                    //                  AT91C_PC17_D17          |\
                                                    //                  AT91C_PC25_D25          |\
                                                    //                  AT91C_PC18_D18          |\
                                                    //                  AT91C_PC26_D26          |\
                                                    //                  AT91C_PC19_D19          |\
                                                    //                  AT91C_PC27_D27          |\
                                                    //                  AT91C_PC28_D28          |\
                                                    //                  AT91C_PC29_D29 
  __writeMemory32(0x85227259,0xFFFFEA08,"Memory");  // AT91C_SDRAMC_CR= AT91C_SDRAMC_NC_9       |\
                                                    //  						    AT91C_SDRAMC_NR_13      |\
                                                    //  						    AT91C_SDRAMC_CAS_2      |\
                                                    //  						    AT91C_SDRAMC_NB_4_BANKS |\
                                                    //  						    AT91C_SDRAMC_DBW_32_BITS|\
                                                    //  						    AT91C_SDRAMC_TWR_2      |\
                                                    //  						    AT91C_SDRAMC_TRC_7      |\
                                                    //						      AT91C_SDRAMC_TRP_2      |\
                                                    //  						    AT91C_SDRAMC_TRCD_2     |\
                                                    //  						    AT91C_SDRAMC_TRAS_5     |\
                                                    //  						    AT91C_SDRAMC_TXSR_8
  __sleep(100);  // wait 100us  
  __writeMemory32(0x00000002,0xFFFFEA00,"Memory");  // AT91C_SDRAMC_MR= AT91C_SDRAMC_MODE_PRCGALL_CMD
  __sleep(200);  // wait 200us  
  // x8
  __writeMemory32(0x00000004,0xFFFFEA00,"Memory");  // AT91C_SDRAMC_MR= AT91C_SDRAMC_MODE_RFSH_CMD
  __writeMemory32(0x00000004,0xFFFFEA00,"Memory");  // AT91C_SDRAMC_MR= AT91C_SDRAMC_MODE_RFSH_CMD
  __writeMemory32(0x00000004,0xFFFFEA00,"Memory");  // AT91C_SDRAMC_MR= AT91C_SDRAMC_MODE_RFSH_CMD
  __writeMemory32(0x00000004,0xFFFFEA00,"Memory");  // AT91C_SDRAMC_MR= AT91C_SDRAMC_MODE_RFSH_CMD
  __writeMemory32(0x00000004,0xFFFFEA00,"Memory");  // AT91C_SDRAMC_MR= AT91C_SDRAMC_MODE_RFSH_CMD
  __writeMemory32(0x00000004,0xFFFFEA00,"Memory");  // AT91C_SDRAMC_MR= AT91C_SDRAMC_MODE_RFSH_CMD
  __writeMemory32(0x00000004,0xFFFFEA00,"Memory");  // AT91C_SDRAMC_MR= AT91C_SDRAMC_MODE_RFSH_CMD
  __writeMemory32(0x00000004,0xFFFFEA00,"Memory");  // AT91C_SDRAMC_MR= AT91C_SDRAMC_MODE_RFSH_CMD

  __writeMemory32(0x00000003,0xFFFFEA00,"Memory");  // AT91C_SDRAMC_MR= AT91C_SDRAMC_MODE_LMR_CMD
  __writeMemory32(0xcafedede,0x20000000,"Memory");  // set SDRAM mode register
  __writeMemory32(700       ,0xFFFFEA04,"Memory");  // AT91C_SDRAMC_TR= 700
  __writeMemory32(0x00000000,0xFFFFEA00,"Memory");  // AT91C_SDRAMC_MR= AT91C_SDRAMC_MODE_NORMAL_CMD
  
  // ******************************************************
  // Test and set Remap
  // ******************************************************
  hold = __readMemory32(0x00000000,"Memory");
  __writeMemory32(0xAAAAAAAA,0x00000000,"Memory");
  if(__readMemory32(0x00000000,"Memory") != 0xAAAAAAAA)
  {
    __writeMemory32(0x03,0xFFFFEE00,"Memory");    // toggle remap bits
  }
  else
  {
    __writeMemory32(hold,0x00000000,"Memory");
  }  
}


execUserPreload()
{
  setup();
  __message("Target init macro complete");
}