at91sam9260.tcl
来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· TCL 代码 · 共 1,163 行 · 第 1/5 页
TCL
1,163 行
set AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES [expr 0x2 << 12 ]
# -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------
set AT91C_SDRAMC_RES [expr 0x1 << 0 ]
# -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------
set AT91C_SDRAMC_RES [expr 0x1 << 0 ]
# -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------
set AT91C_SDRAMC_RES [expr 0x1 << 0 ]
# -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register --------
set AT91C_SDRAMC_RES [expr 0x1 << 0 ]
# -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register --------
set AT91C_SDRAMC_MD [expr 0x3 << 0 ]
set AT91C_SDRAMC_MD_SDRAM 0x0
set AT91C_SDRAMC_MD_LOW_POWER_SDRAM 0x1
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Static Memory Controller Interface
# *****************************************************************************
# -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x --------
set AT91C_SMC_NWESETUP [expr 0x3F << 0 ]
set AT91C_SMC_NCSSETUPWR [expr 0x3F << 8 ]
set AT91C_SMC_NRDSETUP [expr 0x3F << 16 ]
set AT91C_SMC_NCSSETUPRD [expr 0x3F << 24 ]
# -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x --------
set AT91C_SMC_NWEPULSE [expr 0x7F << 0 ]
set AT91C_SMC_NCSPULSEWR [expr 0x7F << 8 ]
set AT91C_SMC_NRDPULSE [expr 0x7F << 16 ]
set AT91C_SMC_NCSPULSERD [expr 0x7F << 24 ]
# -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x --------
set AT91C_SMC_NWECYCLE [expr 0x1FF << 0 ]
set AT91C_SMC_NRDCYCLE [expr 0x1FF << 16 ]
# -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x --------
set AT91C_SMC_READMODE [expr 0x1 << 0 ]
set AT91C_SMC_WRITEMODE [expr 0x1 << 1 ]
set AT91C_SMC_NWAITM [expr 0x3 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_DISABLE [expr 0x0 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN [expr 0x2 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_ENABLE_READY [expr 0x3 << 5 ]
set AT91C_SMC_BAT [expr 0x1 << 8 ]
set AT91C_SMC_BAT_BYTE_SELECT [expr 0x0 << 8 ]
set AT91C_SMC_BAT_BYTE_WRITE [expr 0x1 << 8 ]
set AT91C_SMC_DBW [expr 0x3 << 12 ]
set AT91C_SMC_DBW_WIDTH_EIGTH_BITS [expr 0x0 << 12 ]
set AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS [expr 0x1 << 12 ]
set AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS [expr 0x2 << 12 ]
set AT91C_SMC_TDF [expr 0xF << 16 ]
set AT91C_SMC_TDFEN [expr 0x1 << 20 ]
set AT91C_SMC_PMEN [expr 0x1 << 24 ]
set AT91C_SMC_PS [expr 0x3 << 28 ]
set AT91C_SMC_PS_SIZE_FOUR_BYTES [expr 0x0 << 28 ]
set AT91C_SMC_PS_SIZE_EIGHT_BYTES [expr 0x1 << 28 ]
set AT91C_SMC_PS_SIZE_SIXTEEN_BYTES [expr 0x2 << 28 ]
set AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES [expr 0x3 << 28 ]
# -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x --------
set AT91C_SMC_NWESETUP [expr 0x3F << 0 ]
set AT91C_SMC_NCSSETUPWR [expr 0x3F << 8 ]
set AT91C_SMC_NRDSETUP [expr 0x3F << 16 ]
set AT91C_SMC_NCSSETUPRD [expr 0x3F << 24 ]
# -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x --------
set AT91C_SMC_NWEPULSE [expr 0x7F << 0 ]
set AT91C_SMC_NCSPULSEWR [expr 0x7F << 8 ]
set AT91C_SMC_NRDPULSE [expr 0x7F << 16 ]
set AT91C_SMC_NCSPULSERD [expr 0x7F << 24 ]
# -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x --------
set AT91C_SMC_NWECYCLE [expr 0x1FF << 0 ]
set AT91C_SMC_NRDCYCLE [expr 0x1FF << 16 ]
# -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x --------
set AT91C_SMC_READMODE [expr 0x1 << 0 ]
set AT91C_SMC_WRITEMODE [expr 0x1 << 1 ]
set AT91C_SMC_NWAITM [expr 0x3 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_DISABLE [expr 0x0 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN [expr 0x2 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_ENABLE_READY [expr 0x3 << 5 ]
set AT91C_SMC_BAT [expr 0x1 << 8 ]
set AT91C_SMC_BAT_BYTE_SELECT [expr 0x0 << 8 ]
set AT91C_SMC_BAT_BYTE_WRITE [expr 0x1 << 8 ]
set AT91C_SMC_DBW [expr 0x3 << 12 ]
set AT91C_SMC_DBW_WIDTH_EIGTH_BITS [expr 0x0 << 12 ]
set AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS [expr 0x1 << 12 ]
set AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS [expr 0x2 << 12 ]
set AT91C_SMC_TDF [expr 0xF << 16 ]
set AT91C_SMC_TDFEN [expr 0x1 << 20 ]
set AT91C_SMC_PMEN [expr 0x1 << 24 ]
set AT91C_SMC_PS [expr 0x3 << 28 ]
set AT91C_SMC_PS_SIZE_FOUR_BYTES [expr 0x0 << 28 ]
set AT91C_SMC_PS_SIZE_EIGHT_BYTES [expr 0x1 << 28 ]
set AT91C_SMC_PS_SIZE_SIXTEEN_BYTES [expr 0x2 << 28 ]
set AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES [expr 0x3 << 28 ]
# -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x --------
set AT91C_SMC_NWESETUP [expr 0x3F << 0 ]
set AT91C_SMC_NCSSETUPWR [expr 0x3F << 8 ]
set AT91C_SMC_NRDSETUP [expr 0x3F << 16 ]
set AT91C_SMC_NCSSETUPRD [expr 0x3F << 24 ]
# -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x --------
set AT91C_SMC_NWEPULSE [expr 0x7F << 0 ]
set AT91C_SMC_NCSPULSEWR [expr 0x7F << 8 ]
set AT91C_SMC_NRDPULSE [expr 0x7F << 16 ]
set AT91C_SMC_NCSPULSERD [expr 0x7F << 24 ]
# -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x --------
set AT91C_SMC_NWECYCLE [expr 0x1FF << 0 ]
set AT91C_SMC_NRDCYCLE [expr 0x1FF << 16 ]
# -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x --------
set AT91C_SMC_READMODE [expr 0x1 << 0 ]
set AT91C_SMC_WRITEMODE [expr 0x1 << 1 ]
set AT91C_SMC_NWAITM [expr 0x3 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_DISABLE [expr 0x0 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN [expr 0x2 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_ENABLE_READY [expr 0x3 << 5 ]
set AT91C_SMC_BAT [expr 0x1 << 8 ]
set AT91C_SMC_BAT_BYTE_SELECT [expr 0x0 << 8 ]
set AT91C_SMC_BAT_BYTE_WRITE [expr 0x1 << 8 ]
set AT91C_SMC_DBW [expr 0x3 << 12 ]
set AT91C_SMC_DBW_WIDTH_EIGTH_BITS [expr 0x0 << 12 ]
set AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS [expr 0x1 << 12 ]
set AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS [expr 0x2 << 12 ]
set AT91C_SMC_TDF [expr 0xF << 16 ]
set AT91C_SMC_TDFEN [expr 0x1 << 20 ]
set AT91C_SMC_PMEN [expr 0x1 << 24 ]
set AT91C_SMC_PS [expr 0x3 << 28 ]
set AT91C_SMC_PS_SIZE_FOUR_BYTES [expr 0x0 << 28 ]
set AT91C_SMC_PS_SIZE_EIGHT_BYTES [expr 0x1 << 28 ]
set AT91C_SMC_PS_SIZE_SIXTEEN_BYTES [expr 0x2 << 28 ]
set AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES [expr 0x3 << 28 ]
# -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x --------
set AT91C_SMC_NWESETUP [expr 0x3F << 0 ]
set AT91C_SMC_NCSSETUPWR [expr 0x3F << 8 ]
set AT91C_SMC_NRDSETUP [expr 0x3F << 16 ]
set AT91C_SMC_NCSSETUPRD [expr 0x3F << 24 ]
# -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x --------
set AT91C_SMC_NWEPULSE [expr 0x7F << 0 ]
set AT91C_SMC_NCSPULSEWR [expr 0x7F << 8 ]
set AT91C_SMC_NRDPULSE [expr 0x7F << 16 ]
set AT91C_SMC_NCSPULSERD [expr 0x7F << 24 ]
# -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x --------
set AT91C_SMC_NWECYCLE [expr 0x1FF << 0 ]
set AT91C_SMC_NRDCYCLE [expr 0x1FF << 16 ]
# -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x --------
set AT91C_SMC_READMODE [expr 0x1 << 0 ]
set AT91C_SMC_WRITEMODE [expr 0x1 << 1 ]
set AT91C_SMC_NWAITM [expr 0x3 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_DISABLE [expr 0x0 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN [expr 0x2 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_ENABLE_READY [expr 0x3 << 5 ]
set AT91C_SMC_BAT [expr 0x1 << 8 ]
set AT91C_SMC_BAT_BYTE_SELECT [expr 0x0 << 8 ]
set AT91C_SMC_BAT_BYTE_WRITE [expr 0x1 << 8 ]
set AT91C_SMC_DBW [expr 0x3 << 12 ]
set AT91C_SMC_DBW_WIDTH_EIGTH_BITS [expr 0x0 << 12 ]
set AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS [expr 0x1 << 12 ]
set AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS [expr 0x2 << 12 ]
set AT91C_SMC_TDF [expr 0xF << 16 ]
set AT91C_SMC_TDFEN [expr 0x1 << 20 ]
set AT91C_SMC_PMEN [expr 0x1 << 24 ]
set AT91C_SMC_PS [expr 0x3 << 28 ]
set AT91C_SMC_PS_SIZE_FOUR_BYTES [expr 0x0 << 28 ]
set AT91C_SMC_PS_SIZE_EIGHT_BYTES [expr 0x1 << 28 ]
set AT91C_SMC_PS_SIZE_SIXTEEN_BYTES [expr 0x2 << 28 ]
set AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES [expr 0x3 << 28 ]
# -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x --------
set AT91C_SMC_NWESETUP [expr 0x3F << 0 ]
set AT91C_SMC_NCSSETUPWR [expr 0x3F << 8 ]
set AT91C_SMC_NRDSETUP [expr 0x3F << 16 ]
set AT91C_SMC_NCSSETUPRD [expr 0x3F << 24 ]
# -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x --------
set AT91C_SMC_NWEPULSE [expr 0x7F << 0 ]
set AT91C_SMC_NCSPULSEWR [expr 0x7F << 8 ]
set AT91C_SMC_NRDPULSE [expr 0x7F << 16 ]
set AT91C_SMC_NCSPULSERD [expr 0x7F << 24 ]
# -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x --------
set AT91C_SMC_NWECYCLE [expr 0x1FF << 0 ]
set AT91C_SMC_NRDCYCLE [expr 0x1FF << 16 ]
# -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x --------
set AT91C_SMC_READMODE [expr 0x1 << 0 ]
set AT91C_SMC_WRITEMODE [expr 0x1 << 1 ]
set AT91C_SMC_NWAITM [expr 0x3 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_DISABLE [expr 0x0 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN [expr 0x2 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_ENABLE_READY [expr 0x3 << 5 ]
set AT91C_SMC_BAT [expr 0x1 << 8 ]
set AT91C_SMC_BAT_BYTE_SELECT [expr 0x0 << 8 ]
set AT91C_SMC_BAT_BYTE_WRITE [expr 0x1 << 8 ]
set AT91C_SMC_DBW [expr 0x3 << 12 ]
set AT91C_SMC_DBW_WIDTH_EIGTH_BITS [expr 0x0 << 12 ]
set AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS [expr 0x1 << 12 ]
set AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS [expr 0x2 << 12 ]
set AT91C_SMC_TDF [expr 0xF << 16 ]
set AT91C_SMC_TDFEN [expr 0x1 << 20 ]
set AT91C_SMC_PMEN [expr 0x1 << 24 ]
set AT91C_SMC_PS [expr 0x3 << 28 ]
set AT91C_SMC_PS_SIZE_FOUR_BYTES [expr 0x0 << 28 ]
set AT91C_SMC_PS_SIZE_EIGHT_BYTES [expr 0x1 << 28 ]
set AT91C_SMC_PS_SIZE_SIXTEEN_BYTES [expr 0x2 << 28 ]
set AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES [expr 0x3 << 28 ]
# -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x --------
set AT91C_SMC_NWESETUP [expr 0x3F << 0 ]
set AT91C_SMC_NCSSETUPWR [expr 0x3F << 8 ]
set AT91C_SMC_NRDSETUP [expr 0x3F << 16 ]
set AT91C_SMC_NCSSETUPRD [expr 0x3F << 24 ]
# -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x --------
set AT91C_SMC_NWEPULSE [expr 0x7F << 0 ]
set AT91C_SMC_NCSPULSEWR [expr 0x7F << 8 ]
set AT91C_SMC_NRDPULSE [expr 0x7F << 16 ]
set AT91C_SMC_NCSPULSERD [expr 0x7F << 24 ]
# -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x --------
set AT91C_SMC_NWECYCLE [expr 0x1FF << 0 ]
set AT91C_SMC_NRDCYCLE [expr 0x1FF << 16 ]
# -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x --------
set AT91C_SMC_READMODE [expr 0x1 << 0 ]
set AT91C_SMC_WRITEMODE [expr 0x1 << 1 ]
set AT91C_SMC_NWAITM [expr 0x3 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_DISABLE [expr 0x0 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN [expr 0x2 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_ENABLE_READY [expr 0x3 << 5 ]
set AT91C_SMC_BAT [expr 0x1 << 8 ]
set AT91C_SMC_BAT_BYTE_SELECT [expr 0x0 << 8 ]
set AT91C_SMC_BAT_BYTE_WRITE [expr 0x1 << 8 ]
set AT91C_SMC_DBW [expr 0x3 << 12 ]
set AT91C_SMC_DBW_WIDTH_EIGTH_BITS [expr 0x0 << 12 ]
set AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS [expr 0x1 << 12 ]
set AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS [expr 0x2 << 12 ]
set AT91C_SMC_TDF [expr 0xF << 16 ]
set AT91C_SMC_TDFEN [expr 0x1 << 20 ]
set AT91C_SMC_PMEN [expr 0x1 << 24 ]
set AT91C_SMC_PS [expr 0x3 << 28 ]
set AT91C_SMC_PS_SIZE_FOUR_BYTES [expr 0x0 << 28 ]
set AT91C_SMC_PS_SIZE_EIGHT_BYTES [expr 0x1 << 28 ]
set AT91C_SMC_PS_SIZE_SIXTEEN_BYTES [expr 0x2 << 28 ]
set AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES [expr 0x3 << 28 ]
# -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x --------
set AT91C_SMC_NWESETUP [expr 0x3F << 0 ]
set AT91C_SMC_NCSSETUPWR [expr 0x3F << 8 ]
set AT91C_SMC_NRDSETUP [expr 0x3F << 16 ]
set AT91C_SMC_NCSSETUPRD [expr 0x3F << 24 ]
# -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x --------
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?