sam9_sdram.mac

来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· MAC 代码 · 共 365 行 · 第 1/2 页

// ---------------------------------------------------------
//   ATMEL Microcontroller Software Support  -  ROUSSET  -
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any  kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
//  File: SAM9_SDRAM.mac
//  User setup file for CSPY debugger.
//  1.1 08/Aug/06 jpp    : Creation
//
//  $Revision: 14949 $
//
// ---------------------------------------------------------
__var __mac_i;
__var __mac_pt;

/*********************************************************************
*
*       execUserReset() : JTAG set initially to Full Speed
*/
execUserReset()
{
    __message "------------------------------ execUserReset ---------------------------------";
    CheckNoRemap();
    ini();
    __PllSetting100MHz();              
    __AIC();                          //* Init AIC
    __message "-------------------------------Set PC Reset ----------------------------------";
    __writeMemory32(0xD3,0x98,"Register");        //*  Set CPSR
    __writeMemory32(0x20000000,0xB4,"Register");  //*  Set PC (R15)

}

/*********************************************************************
*
*       execUserPreload() : JTAG set initially to 32kHz
*/
execUserPreload()
{
    __message "------------------------------ execUserPreload ---------------------------------";
    __writeMemory32(0xD3,0x98,"Register"); //*  Set CPSR
    __PllSetting();                   //* Init PLL
    __PllSetting100MHz();              
    __initSDRAM();                    //* Init SDRAM before load
    __AIC();                          //* Init AIC
    CheckNoRemap();                   //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
    Watchdog();                       //* Watchdog Disable

//*  Get the Chip ID  (AT91C_DBGU_C1R & AT91C_DBGU_C2R
    __mac_i=__readMemory32(0xFFFFF240,"Memory");
    __message " ---------------------------------------- Chip ID   0x",__mac_i:%X;

    if ( __mac_i == 0x019803A1)  {__message " Chip ID for AT91SAM9260";}
    else { __message " Chip ID for unknown !!";}
    __mac_i=__readMemory32(0xFFFFF244,"Memory");
    __message " ---------------------------------------- Extention 0x",__mac_i:%X;

}
/*********************************************************************
*
*       __initSDRAM()
* Function description
* Set SDRAM for works at 100 MHz
*/
__initSDRAM()
{
__var SDRAM_BaseAdddr, i;

  SDRAM_BaseAdddr = 0x20000000;                             // CS1 SDRAM


  // Bus matrix init
  i = __readMemory32(0xFFFFEF1C,"Memory");
  __writeMemory32(i | 0x00010002,0xFFFFEF1C,"Memory");      // Enable SDRAM CS


  // assign IO to SDRAM controller
  __writeMemory32(      1<<4,0xFFFFFC10,"Memory");          // Enable PORTC peripheral clock
  __writeMemory32(0xFFFF0000,0xFFFFF854,"Memory");          // PORC Multi diver disable
  __writeMemory32(0xFFFF0000,0xFFFFF870,"Memory");          // PORC Peripheral A function select
  __writeMemory32(0xFFFF0000,0xFFFFF804,"Memory");          // PORC Controller PIO Disable


  // Init SDRAM sequency
  // 1. SDRAM features must be set in the configuration register: asynchronous timings
  // (TRC, TRAS, ...), number of column, rows, CAS latency, and the data bus width.
  __writeMemory32(1,0xFFFFEA00,"Memory");                   // SDRAMC_MR - NOP
  __writeMemory32(780,0xFFFFEA04,"Memory");                 // SDRAMC_TR
  __writeMemory32((1 << 0) |  /* Col - 9                                      */
                  (2 << 2) |  /* Row - 13                                     */
                  (1 << 4) |  /* 4 Banks                                      */
                  (2 << 5) |  /* CAS - 2                                      */
                  (0 << 7) |  /* Data Bus  32bits                             */
                  (2 << 8) |  /* twr - 1clk + 7.5 ns                          */
                  (7 <<12) |  /* trc - 66 ns                                  */
                  (2 <<16) |  /* trp - 20 ns                                  */
                  (2 <<20) |  /* trcd - 20 ns                                 */
                  (5 <<24) |  /* tras - 44 ns                                 */
                  (8 <<28),0xFFFFEA08,"Memory");          // SDRAMC_CR
  __writeMemory32(0,0xFFFFEA10,"Memory");                   // SDRAMC_LPR
  __writeMemory32(0,0xFFFFEA24,"Memory");                   // SDRAMC_MDR
  // 2. A minimum pause of 200 us is provided to precede any signal toggle.
  __sleep(200);
  __writeMemory32(0,SDRAM_BaseAdddr,"Memory");              // NOP
  __sleep(100);
  // 3. An All Banks Precharge command is issued to the SDRAM devices. The application
  // must set Mode to 2 in the Mode Register and perform a write access to any SDRAM address.
  __writeMemory32(2,0xFFFFEA00,"Memory");                   // SDRAMC_MR - PRECHARGEALL
  __writeMemory32(1,SDRAM_BaseAdddr,"Memory");

  // 6. Eight auto-refresh (CBR) cycles are provided. The application must set the Mode to 4
  // in the Mode Register and performs a write access to any SDRAM location height times.
  __writeMemory32(4,0xFFFFEA00,"Memory");                   // SDRAMC_MR - AUTOREFRESH
  for(i = 0; i < 8 ;++i)
  {
    __writeMemory32(i,SDRAM_BaseAdddr,"Memory");
  }
  // 7. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRAM
  // devices, in particular CAS latency and burst length. The application must set Mode to
  // 3 in the Mode Register and perform a write access to the SDRAM. The write address
  // must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB
  // SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access
  // should be done at the address 0x20000000.
  __writeMemory32(3,0xFFFFEA00,"Memory");                   // SDRAMC_MR - SET MODE REGISTER
  // When you perform a write after a "load mode register" command, the correct
  // adress offset is hard coded by the SDRAM Controller. So whatever the value
  // you write it will not take into account.
  __writeMemory32(0x55555555,SDRAM_BaseAdddr,"Memory");
  // 8. For mobile SDRAM initialization, an Extended Mode Register set (EMRS) cycle is
  // issued to program the SDRAM parameters (TCSR, PASR, DS). The application must
  // set Mode to 5 in the Mode Register and perform a write access to the SDRAM. The
  // write address must be chosen so that BA[1] or BA[0] are set to 1. For example, with a
  // 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank address the SDRAM
  // write access should be done at the address 0x20800000 or 0x20400000.
  // 9. The application must go into Normal Mode, setting Mode to 0 in the Mode Register
  // and performing a write access at any location in the SDRAM.
  __writeMemory32(0,0xFFFFEA00,"Memory");                   // SDRAMC_MR - NORM MODE
  __writeMemory32(0xababcafe,SDRAM_BaseAdddr,"Memory");
  // 10. Write the refresh rate into the count field in the SDRAMC Refresh Timer register.
  // (Refresh rate = delay between refresh cycles). The SDRAM device requires a refresh
  // every 15.625 us or 7.81 us. With a 100 MHz frequency, the Refresh Timer Counter
  // Register must be set with the value 1562(15.652 us x 100 MHz) or 781(7.81 us x 100MHz).
 
   __message "------------------------------- SDRAM Done at 100 MHz -------------------------------";

}

/*********************************************************************
*
*       __PllSetting()
* Function description
*   Initializes the PMC.
*   1. Enable the Main Oscillator
*   2. Configure PLL
*   3. Switch Master
*/
__PllSetting()
{
     if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) {
//* Disable all PMC interrupt ( $$ JPP)
//* AT91C_PMC_IDR   ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
//*    pPmc->PMC_IDR = 0xFFFFFFFF;
    __writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory");
//* AT91C_PMC_PCDR  ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
    __writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory");
// Disable all clock only Processor clock is enabled.
    __writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory");

// AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
    __writeMemory32(0x00000001,0xFFFFFC30,"Memory");
    __sleep(10000);

// write reset value to PLLA and PLLB
// AT91C_PMC_PLLAR ((AT91_REG *) 	0xFFFFFC28) // (PMC) PLL A Register
    __writeMemory32(0x00003F00,0xFFFFFC28,"Memory");

// AT91C_PMC_PLLBR ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL B Register
    __writeMemory32(0x00003F00,0xFFFFFC2C,"Memory");
    __sleep(10000);