at91sam9261_sdramc.h

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/* linux/include/asm-arm/arch-at91sam9261/at91sam9261_sdramc.h
 * 
 * Hardware definition for the sdramc peripheral in the ATMEL at91sam9261 processor
 * 
 * Generated  12/07/2006 (13:13:27) AT91 SW Application Group from HSDRAMC1_6100A V1.2
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */


#ifndef __AT91SAM9261_SDRAMC_H
#define __AT91SAM9261_SDRAMC_H

/* -------------------------------------------------------- */
/* SDRAMC ID definitions for  AT91SAM9261           */
/* -------------------------------------------------------- */
#ifndef AT91C_ID_SYS
#define AT91C_ID_SYS   	 1 /**< System Interrupt id */
#endif /* AT91C_ID_SYS */

/* -------------------------------------------------------- */
/* SDRAMC Base Address definitions for  AT91SAM9261   */
/* -------------------------------------------------------- */
#define AT91C_BASE_SDRAMC    	0xFFFFEA00 /**< SDRAMC base address */

/* -------------------------------------------------------- */
/* PIO definition for SDRAMC hardware peripheral */
/* -------------------------------------------------------- */
#define AT91C_PC16_D16      	(1 << 16) /**< Data Bus [16] */
#define AT91C_PC17_D17      	(1 << 17) /**< Data Bus [17] */
#define AT91C_PC18_D18      	(1 << 18) /**< Data Bus [18] */
#define AT91C_PC19_D19      	(1 << 19) /**< Data Bus [19] */
#define AT91C_PC20_D20      	(1 << 20) /**< Data Bus [20] */
#define AT91C_PC21_D21      	(1 << 21) /**< Data Bus [21] */
#define AT91C_PC22_D22      	(1 << 22) /**< Data Bus [22] */
#define AT91C_PC23_D23      	(1 << 23) /**< Data Bus [23] */
#define AT91C_PC24_D24      	(1 << 24) /**< Data Bus [24] */
#define AT91C_PC25_D25      	(1 << 25) /**< Data Bus [25] */
#define AT91C_PC26_D26      	(1 << 26) /**< Data Bus [26] */
#define AT91C_PC27_D27      	(1 << 27) /**< Data Bus [27] */
#define AT91C_PC28_D28      	(1 << 28) /**< Data Bus [28] */
#define AT91C_PC29_D29      	(1 << 29) /**< Data Bus [29] */
#define AT91C_PC30_D30      	(1 << 30) /**< Data Bus [30] */
#define AT91C_PC31_D31      	(1 << 31) /**< Data Bus [31] */


/* -------------------------------------------------------- */
/* Register offset definition for SDRAMC hardware peripheral */
/* -------------------------------------------------------- */
#define SDRAMC_MR 	(0x0000) 	/**< SDRAM Controller Mode Register */
#define SDRAMC_TR 	(0x0004) 	/**< SDRAM Controller Refresh Timer Register */
#define SDRAMC_CR 	(0x0008) 	/**< SDRAM Controller Configuration Register */
#define SDRAMC_HSR 	(0x000C) 	/**< SDRAM Controller High Speed Register */
#define SDRAMC_LPR 	(0x0010) 	/**< SDRAM Controller Low Power Register */
#define SDRAMC_IER 	(0x0014) 	/**< SDRAM Controller Interrupt Enable Register */
#define SDRAMC_IDR 	(0x0018) 	/**< SDRAM Controller Interrupt Disable Register */
#define SDRAMC_IMR 	(0x001C) 	/**< SDRAM Controller Interrupt Mask Register */
#define SDRAMC_ISR 	(0x0020) 	/**< SDRAM Controller Interrupt Mask Register */
#define SDRAMC_MDR 	(0x0024) 	/**< SDRAM Memory Device Register */

/* -------------------------------------------------------- */
/* Bitfields definition for SDRAMC hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register SDRAMC_MR */
#define AT91C_SDRAMC_MODE     (0xF << 0 ) /**< (SDRAMC) Mode */
#define 	AT91C_SDRAMC_MODE_NORMAL_CMD           0x0 /**< (SDRAMC) Normal Mode */
#define 	AT91C_SDRAMC_MODE_NOP_CMD              0x1 /**< (SDRAMC) Issue a NOP Command at every access */
#define 	AT91C_SDRAMC_MODE_PRCGALL_CMD          0x2 /**< (SDRAMC) Issue a All Banks Precharge Command at every access */
#define 	AT91C_SDRAMC_MODE_LMR_CMD              0x3 /**< (SDRAMC) Issue a Load Mode Register at every access */
#define 	AT91C_SDRAMC_MODE_RFSH_CMD             0x4 /**< (SDRAMC) Issue a Refresh */
#define 	AT91C_SDRAMC_MODE_EXT_LMR_CMD          0x5 /**< (SDRAMC) Issue an Extended Load Mode Register */
#define 	AT91C_SDRAMC_MODE_DEEP_CMD             0x6 /**< (SDRAMC) Enter Deep Power Mode */
/* --- Register SDRAMC_TR */
#define AT91C_SDRAMC_COUNT    (0xFFF << 0 ) /**< (SDRAMC) Refresh Counter */
/* --- Register SDRAMC_CR */
#define AT91C_SDRAMC_NC       (0x3 << 0 ) /**< (SDRAMC) Number of Column Bits */
#define 	AT91C_SDRAMC_NC_8                    0x0 /**< (SDRAMC) 8 Bits */
#define 	AT91C_SDRAMC_NC_9                    0x1 /**< (SDRAMC) 9 Bits */
#define 	AT91C_SDRAMC_NC_10                   0x2 /**< (SDRAMC) 10 Bits */
#define 	AT91C_SDRAMC_NC_11                   0x3 /**< (SDRAMC) 11 Bits */
#define AT91C_SDRAMC_NR       (0x3 << 2 ) /**< (SDRAMC) Number of Row Bits */
#define 	AT91C_SDRAMC_NR_11                   (0x0 <<  2) /**< (SDRAMC) 11 Bits */
#define 	AT91C_SDRAMC_NR_12                   (0x1 <<  2) /**< (SDRAMC) 12 Bits */
#define 	AT91C_SDRAMC_NR_13                   (0x2 <<  2) /**< (SDRAMC) 13 Bits */
#define AT91C_SDRAMC_NB       (0x1 << 4 ) /**< (SDRAMC) Number of Banks */
#define 	AT91C_SDRAMC_NB_2_BANKS              (0x0 <<  4) /**< (SDRAMC) 2 banks */
#define 	AT91C_SDRAMC_NB_4_BANKS              (0x1 <<  4) /**< (SDRAMC) 4 banks */
#define AT91C_SDRAMC_CAS      (0x3 << 5 ) /**< (SDRAMC) CAS Latency */
#define 	AT91C_SDRAMC_CAS_2                    (0x2 <<  5) /**< (SDRAMC) 2 cycles */
#define 	AT91C_SDRAMC_CAS_3                    (0x3 <<  5) /**< (SDRAMC) 3 cycles */
#define AT91C_SDRAMC_DBW      (0x1 << 7 ) /**< (SDRAMC) Data Bus Width */
#define 	AT91C_SDRAMC_DBW_32_BITS              (0x0 <<  7) /**< (SDRAMC) 32 Bits datas bus */
#define 	AT91C_SDRAMC_DBW_16_BITS              (0x1 <<  7) /**< (SDRAMC) 16 Bits datas bus */
#define AT91C_SDRAMC_TWR      (0xF << 8 ) /**< (SDRAMC) Number of Write Recovery Time Cycles */
#define 	AT91C_SDRAMC_TWR_0                    (0x0 <<  8) /**< (SDRAMC) Value :  0 */
#define 	AT91C_SDRAMC_TWR_1                    (0x1 <<  8) /**< (SDRAMC) Value :  1 */
#define 	AT91C_SDRAMC_TWR_2                    (0x2 <<  8) /**< (SDRAMC) Value :  2 */
#define 	AT91C_SDRAMC_TWR_3                    (0x3 <<  8) /**< (SDRAMC) Value :  3 */
#define 	AT91C_SDRAMC_TWR_4                    (0x4 <<  8) /**< (SDRAMC) Value :  4 */
#define 	AT91C_SDRAMC_TWR_5                    (0x5 <<  8) /**< (SDRAMC) Value :  5 */
#define 	AT91C_SDRAMC_TWR_6                    (0x6 <<  8) /**< (SDRAMC) Value :  6 */
#define 	AT91C_SDRAMC_TWR_7                    (0x7 <<  8) /**< (SDRAMC) Value :  7 */
#define 	AT91C_SDRAMC_TWR_8                    (0x8 <<  8) /**< (SDRAMC) Value :  8 */
#define 	AT91C_SDRAMC_TWR_9                    (0x9 <<  8) /**< (SDRAMC) Value :  9 */
#define 	AT91C_SDRAMC_TWR_10                   (0xA <<  8) /**< (SDRAMC) Value : 10 */