at91sam9261_ssc.h

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/* linux/include/asm-arm/arch-at91sam9261/at91sam9261_ssc.h
 * 
 * Hardware definition for the ssc peripheral in the ATMEL at91sam9261 processor
 * 
 * Generated  12/07/2006 (13:13:27) AT91 SW Application Group from SSC_6078B V1.1
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */


#ifndef __AT91SAM9261_SSC_H
#define __AT91SAM9261_SSC_H

/* -------------------------------------------------------- */
/* SSC ID definitions for  AT91SAM9261           */
/* -------------------------------------------------------- */
#ifndef AT91C_ID_SSC0
#define AT91C_ID_SSC0  	14 /**< Serial Synchronous Controller 0 id */
#endif /* AT91C_ID_SSC0 */
#ifndef AT91C_ID_SSC1
#define AT91C_ID_SSC1  	15 /**< Serial Synchronous Controller 1 id */
#endif /* AT91C_ID_SSC1 */
#ifndef AT91C_ID_SSC2
#define AT91C_ID_SSC2  	16 /**< Serial Synchronous Controller 2 id */
#endif /* AT91C_ID_SSC2 */

/* -------------------------------------------------------- */
/* SSC Base Address definitions for  AT91SAM9261   */
/* -------------------------------------------------------- */
#define AT91C_BASE_SSC0      	0xFFFBC000 /**< SSC0 base address */
#define AT91C_BASE_SSC1      	0xFFFC0000 /**< SSC1 base address */
#define AT91C_BASE_SSC2      	0xFFFC4000 /**< SSC2 base address */

/* -------------------------------------------------------- */
/* PIO definition for SSC hardware peripheral */
/* -------------------------------------------------------- */
#define AT91C_PB24_RD0      	(1 << 24) /**< SSC0 Receive Data */
#define AT91C_PB26_RF0      	(1 << 26) /**< SSC0 Receive Frame Sync */
#define AT91C_PB25_RK0      	(1 << 25) /**< SSC0 Receive Clock */
#define AT91C_PB23_TD0      	(1 << 23) /**< SSC0 Transmit Data */
#define AT91C_PB21_TF0      	(1 << 21) /**< SSC0 Transmit Frame Sync */
#define AT91C_PB22_TK0      	(1 << 22) /**< SSC0 Transmit Clock */

#define AT91C_PA20_RD1      	(1 << 20) /**< SSC1 Receive Data */
#define AT91C_PA22_RF1      	(1 << 22) /**< SSC1 Receive Frame Sync */
#define AT91C_PA21_RK1      	(1 << 21) /**< SSC1 Receive Clock */
#define AT91C_PA19_TD1      	(1 << 19) /**< SSC1 Transmit Data */
#define AT91C_PA17_TF1      	(1 << 17) /**< SSC1 Transmit Frame Sync */
#define AT91C_PA18_TK1      	(1 << 18) /**< SSC1 Transmit Clock */

#define AT91C_PC28_RD2      	(1 << 28) /**< SSC2 Receive Data */
#define AT91C_PC30_RF2      	(1 << 30) /**< SSC2 Receive Frame Sync */
#define AT91C_PC29_RK2      	(1 << 29) /**< SSC2 Receive Clock */
#define AT91C_PC27_TD2      	(1 << 27) /**< SSC2 Transmit Data */
#define AT91C_PC25_TF2      	(1 << 25) /**< SSC2 Transmit Frame Sync */
#define AT91C_PC26_TK2      	(1 << 26) /**< SSC2 Transmit Clock */


/* -------------------------------------------------------- */
/* Register offset definition for SSC hardware peripheral */
/* -------------------------------------------------------- */
#define SSC_CR 	(0x0000) 	/**< Control Register */
#define SSC_CMR 	(0x0004) 	/**< Clock Mode Register */
#define SSC_RCMR 	(0x0010) 	/**< Receive Clock ModeRegister */
#define SSC_RFMR 	(0x0014) 	/**< Receive Frame Mode Register */
#define SSC_TCMR 	(0x0018) 	/**< Transmit Clock Mode Register */
#define SSC_TFMR 	(0x001C) 	/**< Transmit Frame Mode Register */
#define SSC_RHR 	(0x0020) 	/**< Receive Holding Register */
#define SSC_THR 	(0x0024) 	/**< Transmit Holding Register */
#define SSC_RSHR 	(0x0030) 	/**< Receive Sync Holding Register */
#define SSC_TSHR 	(0x0034) 	/**< Transmit Sync Holding Register */
#define SSC_SR 	(0x0040) 	/**< Status Register */
#define SSC_IER 	(0x0044) 	/**< Interrupt Enable Register */
#define SSC_IDR 	(0x0048) 	/**< Interrupt Disable Register */
#define SSC_IMR 	(0x004C) 	/**< Interrupt Mask Register */
#define SSC_RPR 	(0x0100) 	/**< Receive Pointer Register */
#define SSC_RCR 	(0x0104) 	/**< Receive Counter Register */
#define SSC_TPR 	(0x0108) 	/**< Transmit Pointer Register */
#define SSC_TCR 	(0x010C) 	/**< Transmit Counter Register */
#define SSC_RNPR 	(0x0110) 	/**< Receive Next Pointer Register */
#define SSC_RNCR 	(0x0114) 	/**< Receive Next Counter Register */
#define SSC_TNPR 	(0x0118) 	/**< Transmit Next Pointer Register */
#define SSC_TNCR 	(0x011C) 	/**< Transmit Next Counter Register */
#define SSC_PTCR 	(0x0120) 	/**< PDC Transfer Control Register */
#define SSC_PTSR 	(0x0124) 	/**< PDC Transfer Status Register */

/* -------------------------------------------------------- */
/* Bitfields definition for SSC hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register SSC_CR */
#define AT91C_SSC_RXEN        (0x1 << 0 ) /**< (SSC) Receive Enable */
#define AT91C_SSC_RXDIS       (0x1 << 1 ) /**< (SSC) Receive Disable */
#define AT91C_SSC_TXEN        (0x1 << 8 ) /**< (SSC) Transmit Enable */
#define AT91C_SSC_TXDIS       (0x1 << 9 ) /**< (SSC) Transmit Disable */
#define AT91C_SSC_SWRST       (0x1 << 15) /**< (SSC) Software Reset */
/* --- Register SSC_RCMR */
#define AT91C_SSC_CKS         (0x3 << 0 ) /**< (SSC) Receive/Transmit Clock Selection */
#define 	AT91C_SSC_CKS_DIV                  0x0 /**< (SSC) Divided Clock */
#define 	AT91C_SSC_CKS_TK                   0x1 /**< (SSC) TK Clock signal */
#define 	AT91C_SSC_CKS_RK                   0x2 /**< (SSC) RK pin */
#define AT91C_SSC_CKO         (0x7 << 2 ) /**< (SSC) Receive/Transmit Clock Output Mode Selection */
#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) /**< (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) /**< (SSC) Continuous Receive/Transmit Clock RK pin: Output */
#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) /**< (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
#define AT91C_SSC_CKI         (0x1 << 5 ) /**< (SSC) Receive/Transmit Clock Inversion */
#define AT91C_SSC_CKG         (0x3 << 6 ) /**< (SSC) Receive/Transmit Clock Gating Selection */
#define 	AT91C_SSC_CKG_NONE                 (0x0 <<  6) /**< (SSC) Receive/Transmit Clock Gating: None, continuous clock */
#define 	AT91C_SSC_CKG_LOW                  (0x1 <<  6) /**< (SSC) Receive/Transmit Clock enabled only if RF Low */