at91sam9261_lcdc.h

来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· C头文件 代码 · 共 307 行 · 第 1/2 页

/* linux/include/asm-arm/arch-at91sam9261/at91sam9261_lcdc.h
 * 
 * Hardware definition for the lcdc peripheral in the ATMEL at91sam9261 processor
 * 
 * Generated  12/07/2006 (13:13:26) AT91 SW Application Group from LCDC_6063A V1.3
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */


#ifndef __AT91SAM9261_LCDC_H
#define __AT91SAM9261_LCDC_H

/* -------------------------------------------------------- */
/* LCDC ID definitions for  AT91SAM9261           */
/* -------------------------------------------------------- */
#ifndef AT91C_ID_LCDC
#define AT91C_ID_LCDC  	21 /**< LCD Controller id */
#endif /* AT91C_ID_LCDC */

/* -------------------------------------------------------- */
/* LCDC Base Address definitions for  AT91SAM9261   */
/* -------------------------------------------------------- */
#define AT91C_BASE_LCDC      	0x00600000 /**< LCDC base address */
#define AT91C_BASE_LCDC_16B_TFT 	0x00600000 /**< LCDC_16B_TFT base address */

/* -------------------------------------------------------- */
/* PIO definition for LCDC hardware peripheral */
/* -------------------------------------------------------- */
#define AT91C_PB4_LCDCC    	(1 << 4) /**< LCD Contrast Control */
#define AT91C_PB5_LCDD0    	(1 << 5) /**< LCD Data Bus Bit 0 */
#define AT91C_PB6_LCDD1    	(1 << 6) /**< LCD Data Bus Bit 1 */
#define AT91C_PB15_LCDD10   	(1 << 15) /**< LCD Data Bus Bit 10 */
#define AT91C_PB16_LCDD11   	(1 << 16) /**< LCD Data Bus Bit 11 */
#define AT91C_PB17_LCDD12   	(1 << 17) /**< LCD Data Bus Bit 12 */
#define AT91C_PB18_LCDD13   	(1 << 18) /**< LCD Data Bus Bit 13 */
#define AT91C_PB19_LCDD14   	(1 << 19) /**< LCD Data Bus Bit 14 */
#define AT91C_PB20_LCDD15   	(1 << 20) /**< LCD Data Bus Bit 15 */
#define AT91C_PB21_LCDD16   	(1 << 21) /**< LCD Data Bus Bit 16 */
#define AT91C_PB22_LCDD17   	(1 << 22) /**< LCD Data Bus Bit 17 */
#define AT91C_PB23_LCDD18   	(1 << 23) /**< LCD Data Bus Bit 18 */
#define AT91C_PB24_LCDD19   	(1 << 24) /**< LCD Data Bus Bit 19 */
#define AT91C_PB4_LCDD2    	(1 << 4) /**< LCD Data Bus Bit 2 */
#define AT91C_PB25_LCDD20   	(1 << 25) /**< LCD Data Bus Bit 20 */
#define AT91C_PB26_LCDD21   	(1 << 26) /**< LCD Data Bus Bit 21 */
#define AT91C_PB27_LCDD22   	(1 << 27) /**< LCD Data Bus Bit 22 */
#define AT91C_PB28_LCDD23   	(1 << 28) /**< LCD Data Bus Bit 23 */
#define AT91C_PB8_LCDD3    	(1 << 8) /**< LCD Data Bus Bit 3 */
#define AT91C_PB9_LCDD4    	(1 << 9) /**< LCD Data Bus Bit 4 */
#define AT91C_PB10_LCDD5    	(1 << 10) /**< LCD Data Bus Bit 5 */
#define AT91C_PB11_LCDD6    	(1 << 11) /**< LCD Data Bus Bit 6 */
#define AT91C_PB12_LCDD7    	(1 << 12) /**< LCD Data Bus Bit 7 */
#define AT91C_PB13_LCDD8    	(1 << 13) /**< LCD Data Bus Bit 8 */
#define AT91C_PB14_LCDD9    	(1 << 14) /**< LCD Data Bus Bit 9 */
#define AT91C_PB3_LCDDEN   	(1 << 3) /**< LCD Data Enable */
#define AT91C_PB2_LCDDOTCK 	(1 << 2) /**< LCD Dot Clock */
#define AT91C_PB1_LCDHSYNC 	(1 << 1) /**< LCD Horizontal Synchronization */
#define AT91C_PB0_LCDVSYNC 	(1 << 0) /**< LCD Vertical Synchronization */

#define AT91C_PB10_LCDD10   	(1 << 10) /**< LCD Data Bus Bit 10 */
#define AT91C_PB11_LCDD11   	(1 << 11) /**< LCD Data Bus Bit 11 */
#define AT91C_PB12_LCDD12   	(1 << 12) /**< LCD Data Bus Bit 12 */
#define AT91C_PB13_LCDD13   	(1 << 13) /**< LCD Data Bus Bit 13 */
#define AT91C_PB14_LCDD14   	(1 << 14) /**< LCD Data Bus Bit 14 */
#define AT91C_PB15_LCDD15   	(1 << 15) /**< LCD Data Bus Bit 15 */
#define AT91C_PB16_LCDD19   	(1 << 16) /**< LCD Data Bus Bit 19 */
#define AT91C_PB17_LCDD20   	(1 << 17) /**< LCD Data Bus Bit 20 */
#define AT91C_PB18_LCDD21   	(1 << 18) /**< LCD Data Bus Bit 21 */
#define AT91C_PB19_LCDD22   	(1 << 19) /**< LCD Data Bus Bit 22 */
#define AT91C_PB20_LCDD23   	(1 << 20) /**< LCD Data Bus Bit 23 */
#define AT91C_PB5_LCDD3    	(1 << 5) /**< LCD Data Bus Bit 3 */
#define AT91C_PB6_LCDD4    	(1 << 6) /**< LCD Data Bus Bit 4 */
#define AT91C_PB7_LCDD5    	(1 << 7) /**< LCD Data Bus Bit 5 */
#define AT91C_PB8_LCDD6    	(1 << 8) /**< LCD Data Bus Bit 6 */
#define AT91C_PB9_LCDD7    	(1 << 9) /**< LCD Data Bus Bit 7 */


/* -------------------------------------------------------- */
/* Register offset definition for LCDC hardware peripheral */
/* -------------------------------------------------------- */
#define LCDC_BA1 	(0x0000) 	/**< DMA Base Address Register 1 */
#define LCDC_BA2 	(0x0004) 	/**< DMA Base Address Register 2 */
#define LCDC_FRMP1 	(0x0008) 	/**< DMA Frame Pointer Register 1 */
#define LCDC_FRMP2 	(0x000C) 	/**< DMA Frame Pointer Register 2 */
#define LCDC_FRMA1 	(0x0010) 	/**< DMA Frame Address Register 1 */
#define LCDC_FRMA2 	(0x0014) 	/**< DMA Frame Address Register 2 */
#define LCDC_FRMCFG 	(0x0018) 	/**< DMA Frame Configuration Register */
#define LCDC_DMACON 	(0x001C) 	/**< DMA Control Register */
#define LCDC_DMA2DCFG 	(0x0020) 	/**< DMA 2D addressing configuration */
#define LCDC_LCDCON1 	(0x0800) 	/**< LCD Control 1 Register */
#define LCDC_LCDCON2 	(0x0804) 	/**< LCD Control 2 Register */
#define LCDC_TIM1 	(0x0808) 	/**< LCD Timing Config 1 Register */
#define LCDC_TIM2 	(0x080C) 	/**< LCD Timing Config 2 Register */
#define LCDC_LCDFRCFG 	(0x0810) 	/**< LCD Frame Config Register */
#define LCDC_FIFO 	(0x0814) 	/**< LCD FIFO Register */
#define LCDC_MVAL 	(0x0818) 	/**< LCD Mode Toggle Rate Value Register */
#define LCDC_DP1_2 	(0x081C) 	/**< Dithering Pattern DP1_2 Register */
#define LCDC_DP4_7 	(0x0820) 	/**< Dithering Pattern DP4_7 Register */
#define LCDC_DP3_5 	(0x0824) 	/**< Dithering Pattern DP3_5 Register */
#define LCDC_DP2_3 	(0x0828) 	/**< Dithering Pattern DP2_3 Register */
#define LCDC_DP5_7 	(0x082C) 	/**< Dithering Pattern DP5_7 Register */
#define LCDC_DP3_4 	(0x0830) 	/**< Dithering Pattern DP3_4 Register */
#define LCDC_DP4_5 	(0x0834) 	/**< Dithering Pattern DP4_5 Register */
#define LCDC_DP6_7 	(0x0838) 	/**< Dithering Pattern DP6_7 Register */
#define LCDC_PWRCON 	(0x083C) 	/**< Power Control Register */
#define LCDC_CTRSTCON 	(0x0840) 	/**< Contrast Control Register */
#define LCDC_CTRSTVAL 	(0x0844) 	/**< Contrast Value Register */
#define LCDC_IER 	(0x0848) 	/**< Interrupt Enable Register */
#define LCDC_IDR 	(0x084C) 	/**< Interrupt Disable Register */
#define LCDC_IMR 	(0x0850) 	/**< Interrupt Mask Register */
#define LCDC_ISR 	(0x0854) 	/**< Interrupt Enable Register */
#define LCDC_ICR 	(0x0858) 	/**< Interrupt Clear Register */
#define LCDC_GPR 	(0x085C) 	/**< General Purpose Register */
#define LCDC_ITR 	(0x0860) 	/**< Interrupts Test Register */
#define LCDC_IRR 	(0x0864) 	/**< Interrupts Raw Status Register */
#define LCDC_LUT_ENTRY 	(0x0C00) 	/**< LUT Entries Register */

/* -------------------------------------------------------- */
/* Bitfields definition for LCDC hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register LCDC_FRMP1 */
#define AT91C_LCDC_FRMPT1     (0x3FFFFF << 0 ) /**< (LCDC) Frame Pointer Address 1 */
/* --- Register LCDC_FRMP2 */
#define AT91C_LCDC_FRMPT2     (0x1FFFFF << 0 ) /**< (LCDC) Frame Pointer Address 2 */
/* --- Register LCDC_FRMCFG */
#define AT91C_LCDC_FRSIZE     (0x3FFFFF << 0 ) /**< (LCDC) FRAME SIZE */
#define AT91C_LCDC_BLENGTH    (0xF << 24) /**< (LCDC) BURST LENGTH */
/* --- Register LCDC_DMACON */
#define AT91C_LCDC_DMAEN      (0x1 << 0 ) /**< (LCDC) DAM Enable */
#define AT91C_LCDC_DMARST     (0x1 << 1 ) /**< (LCDC) DMA Reset (WO) */
#define AT91C_LCDC_DMABUSY    (0x1 << 2 ) /**< (LCDC) DMA Reset (WO) */
#define AT91C_LCDC_DMAUPDT    (0x1 << 3 ) /**< (LCDC) DMA Configuration Update */
#define AT91C_LCDC_DMA2DEN    (0x1 << 4 ) /**< (LCDC) 2D Addressing Enable */
/* --- Register LCDC_DMA2DCFG */
#define AT91C_LCDC_ADDRINC    (0xFFFF << 0 ) /**< (LCDC) Number of 32b words that the DMA must jump when going to the next line */
#define AT91C_LCDC_PIXELOFF   (0x1F << 24) /**< (LCDC) Offset (in bits) of the first pixel of the screen in the memory word which contain it */