lib_arm920t.h

最新版IAR FOR ARM（EWARM）5.11中的代码例子

// ****************************************************************************
// CP15 Register 0
// 	Read: ID code | cache type
//	Write: Unpredictable

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadIDCode
//* \brief Read ID code register
//*----------------------------------------------------------------------------
inline unsigned int AT91F_ARM_ReadIDCode()
{
	register unsigned int id;
 	asm("MRC p15, 0, id, c0, c0, 0");
 	return id;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadCacheType
//* \brief Read cache type
//*----------------------------------------------------------------------------
inline unsigned int AT91F_ARM_ReadCacheType()
{
	register unsigned int type;
 	asm("MRC p15, 0, type, c0, c0, 1");
 	return type;
}

// ****************************************************************************
// CP15 Register 1
// 	Read: Control
//	Write: Control

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadControl
//* \brief Read Control register
//*----------------------------------------------------------------------------
inline unsigned int AT91F_ARM_ReadControl()
{
	register unsigned int ctl;
 	asm("MRC p15, 0, r0, c1, c0, 0");
 	return ctl;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WriteControl
//* \brief Write Control register
//*----------------------------------------------------------------------------
inline void AT91F_ARM_WriteControl(unsigned int ctl)
{
 	asm("MCR  p15,0,r0,c1,c0,0");
}

// ****************************************************************************
// CP15 Register 2
// 	Read: Translation table Base
//	Write: Translation table Base

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadTTB
//* \brief Read Translation table base register
//*----------------------------------------------------------------------------
inline unsigned int AT91F_ARM_ReadTTB()
{
	register unsigned int ttb;
 	asm("MRC p15, 0, ttb, c2, c0, 0");
 	return ttb;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WriteTTB
//* \brief Write Translation table base  register
//*----------------------------------------------------------------------------
inline void AT91F_ARM_WriteTTB(unsigned int ttb)
{
  ttb &= 0xFFFFC000;
 	asm("MCR p15, 0,r0, c2, c0, 0");
}

// ****************************************************************************
// CP15 Register 3
// 	Read: Read domain access control
//	Write: Write domain access control

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadDomain
//* \brief Read domain access control
//*----------------------------------------------------------------------------
inline unsigned int AT91F_ARM_ReadDomain()
{
	register unsigned int domain;
 	asm("MRC p15, 0, domain, c3, c0, 0");
 	return domain;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WriteDomain
//* \brief Write domain access control
//*----------------------------------------------------------------------------
inline void AT91F_ARM_WriteDomain(unsigned int domain)
{
 	asm("MCR p15, 0, r0, c3, c0, 0");
}

// ****************************************************************************
// CP15 Register 5
// 	Read: Read Fault Status
//	Write: Write Fault Status

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadDataFSR
//* \brief Read data FSR value
//*----------------------------------------------------------------------------
inline unsigned int AT91F_ARM_ReadDataFSR()
{
	register unsigned int dataFSR;
 	asm("MRC p15, 0, dataFSR, c5, c0, 0");
 	return dataFSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WriteDataFSR
//* \brief Write data FSR value
//*----------------------------------------------------------------------------
inline void AT91F_ARM_WriteDataFSR(unsigned int dataFSR)
{
 	asm("MCR p15, 0, dataFSR, c5, c0, 0");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadPrefetchFSR
//* \brief Read prefetch FSR value
//*----------------------------------------------------------------------------
inline unsigned int AT91F_ARM_ReadPrefetchFSR()
{
	register unsigned int prefetchFSR;
 	asm("MRC p15, 0, prefetchFSR, c5, c0, 1");
 	return prefetchFSR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WritePrefetchFSR
//* \brief Write prefetch FSR value
//*----------------------------------------------------------------------------
inline void AT91F_ARM_WritePrefetchFSR(unsigned int prefetchFSR)
{
 	asm("MCR p15, 0, prefetchFSR, c5, c0, 1");
}

// ****************************************************************************
// CP15 Register 6
// 	Read: Read Fault Address
//	Write: Write Fault Address

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_ReadFAR
//* \brief Read FAR data
//*----------------------------------------------------------------------------
inline unsigned int AT91F_ARM_ReadFAR()
{
	register unsigned int dataFAR;
 	asm("MRC p15, 0, dataFAR, c6, c0, 0");
 	return dataFAR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_WriteFAR
//* \brief Write FAR data
//*----------------------------------------------------------------------------
inline void AT91F_ARM_WriteFAR(unsigned int dataFAR)
{
 	asm("MCR p15, 0, dataFAR, c6, c0, 0");
}

// ****************************************************************************
// CP15 Register 7
// 	Read: Unpredictable
//	Write: Cache operations

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_InvalidateIDCache
//* \brief Invalidate ICache and DCache
//*----------------------------------------------------------------------------
inline void AT91F_ARM_InvalidateIDCache()
{
	register unsigned int sbz = 0;
 	asm("MCR p15, 0, sbz, c7, c7, 0");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_InvalidateICache
//* \brief Invalidate ICache
//*----------------------------------------------------------------------------
inline void AT91F_ARM_InvalidateICache()
{
	register unsigned int sbz = 0;
 	asm("MCR p15, 0, r0, c7, c5, 0");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_InvalidateICacheMVA
//* \brief Invalidate ICache single entry (using MVA)
//*----------------------------------------------------------------------------
inline void AT91F_ARM_InvalidateICacheMVA(unsigned int mva)
{
 	asm("MCR p15, 0, (mva & 0xFFFFFFE0), c7, c5, 1");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_PrefetchICacheLine
//* \brief Prefetch ICache line (using MVA)
//*----------------------------------------------------------------------------
inline void AT91F_ARM_PrefetchICacheLine(unsigned int mva)
{
  mva &= 0xFFFFFFE0;
 	asm("MCR p15, 0, r0 , c7, c13, 1");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_InvalidateDCache
//* \brief Invalidate DCache
//*----------------------------------------------------------------------------
inline void AT91F_ARM_InvalidateDCache()
{
	register unsigned int sbz = 0;
 	asm("MCR p15, 0, r0, c7, c6, 0");
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ARM_InvalidateDCacheMVA
//* \brief Invalidate DCache single entry (using MVA)
//*----------------------------------------------------------------------------
inline void AT91F_ARM_InvalidateDCacheMVA(unsigned int mva)
{
 	asm("MCR p15, 0, (mva & 0xFFFFFFE0), c7, c6, 1");