cstartup.s

来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· S 代码 · 共 305 行

;---------------------------------------------------------------
; Version: 1.4 (14-10-2005)
; SpearNet release version
;---------------------------------------------------------------
; Naming covention of labels in this file:
;---------------------------------------------------------------
;  ?xxx   - External labels only accessed from assembler.
;  __xxx  - External labels accessed from or defined in C.
;  xxx    - Labels local to one module (note: this file contains
;           several modules).
;  main   - The starting point of the user program.
;---------------------------------------------------------------

;---------------------------------------------------------------
; Macros and definitions for the whole file
;---------------------------------------------------------------
                            ; Mode, correspords to bits 0-5 in CPSR
MODE_BITS   DEFINE    0x1F  ; Bit mask for mode bits in CPSR
USR_MODE    DEFINE    0x10  ; User mode
FIQ_MODE    DEFINE    0x11  ; Fast Interrupt Request mode
IRQ_MODE    DEFINE    0x12  ; Interrupt Request mode
SVC_MODE    DEFINE    0x13  ; Supervisor mode
ABT_MODE    DEFINE    0x17  ; Abort mode
UND_MODE    DEFINE    0x1B  ; Undefined Instruction mode
SYS_MODE    DEFINE    0x1F  ; System mode

I_Bit       DEFINE    0x80  ; when I bit is set, IRQ is disabled
F_Bit       DEFINE    0x40  ; when F bit is set, FIQ is disabled


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Part one of the system initialization code, 
;; contains low-level
;; initialization.
;;
;; Copyright 2007 IAR Systems. All rights reserved.
;;
;; $Revision: 14134 $
;;

        MODULE  ?cstartup

        ;; Forward declaration of sections.
        SECTION IRQ_STACK:DATA:NOROOT(3)
        SECTION CSTACK:DATA:NOROOT(3)
        SECTION SVC_STACK:DATA:NOROOT(3)

;
; The module in this file are included in the libraries, and may be
; replaced by any user-defined modules that define the PUBLIC symbol
; __iar_program_start or a user defined start symbol.
;
; To override the cstartup defined in the library, simply add your
; modified version to the workbench project.

        SECTION .intvec:CODE:NOROOT(2)

        PUBLIC  __vector
        PUBLIC  __iar_program_start
        EXTERN  Undefined_Handler
        EXTERN  SWI_Handler
        EXTERN  Prefetch_Handler
        EXTERN  Abort_Handler
        EXTERN  IRQ_Handler
        EXTERN  FIQ_Handler

        ARM
__vector:
        ; All default exception handlers (except reset) are
        ; defined as weak symbol definitions.
        ; If a handler is defined by the application it will take precedence.
        LDR     PC,Reset_Addr           ; Reset
        LDR     PC,Undefined_Addr       ; Undefined instructions
        LDR     PC,SWI_Addr             ; Software interrupt (SWI/SVC)
        LDR     PC,Prefetch_Addr        ; Prefetch abort
        LDR     PC,Abort_Addr           ; Data abort
        DCD     0                       ; RESERVED
        LDR     PC,IRQ_Addr             ; IRQ
        LDR     PC,FIQ_Addr             ; FIQ

Reset_Addr:     DCD   __iar_program_start
Undefined_Addr: DCD   Undefined_Handler
SWI_Addr:       DCD   SWI_Handler
Prefetch_Addr:  DCD   Prefetch_Handler
Abort_Addr:     DCD   Abort_Handler
IRQ_Addr:       DCD   IRQ_Handler
FIQ_Addr:       DCD   FIQ_Handler


; --------------------------------------------------
; ?cstartup -- low-level system initialization code.
;
; After a reser execution starts here, the mode is ARM, supervisor
; with interrupts disabled.
;



        SECTION .text:CODE:NOROOT(2)

;        PUBLIC  ?cstartup        
        EXTERN  ?main
        REQUIRE __vector

        ARM        
        
__iar_program_start:        
?cstartup:

;
; Add initialization needed before setup of stackpointers here.
;
  REPT 12
    nop
  ENDR

  bl  COOP_Init
  bl  SDRAM_Init
  bl  SMC_Init
  bl  STACK_Init
  bl  INTS_Init


  msr CPSR_c,#USR_MODE|F_Bit
  b   ?main

;---------------------------------------------------------------
; Interrupt Controller
;---------------------------------------------------------------
IC_CONTROL          equ   0x30000000
;---------------------------------------------------------------
INTS_Init:
;---------------------------------------------------------------
  ;Disable interrupts
  ldr r0,=IC_CONTROL
  ldr r1,=0
  str r1,[r0]
  bx  lr

;---------------------------------------------------------------
COOP_Init:
;---------------------------------------------------------------
#ifdef __ARMVFP__
; Enable the VFP coprocessor.
  mov     r0, #0x40000000                 ; Set EN bit in VFP
  fmxr    fpexc, r0                       ; FPEXC, clear others.

; Disable underflow exceptions by setting flush to zero mode.
; For full IEEE 754 underflow compliance this code should be removed
; and the appropriate exception handler installed.
  mov     r0, #0x01000000                 ; Set FZ bit in VFP
  fmxr    fpscr, r0                       ; FPSCR, clear others.
#endif

  bx  lr
;
; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS.
; The stack segments must be defined in the linker command file,
; and be declared above.
;

;---------------------------------------------------------------
STACK_Init:
;---------------------------------------------------------------
; Initilaize IRQ stack pointer
;---------------------------------------------------------------
  mrs     r0, cpsr                          ; Original PSR value
  bic     r0, r0, #MODE_BITS                ; Clear the mode bits
  orr     r0, r0, #IRQ_MODE                 ; Set IRQ mode bits
  msr     cpsr_c, r0                        ; Change the mode
  ldr     sp, =SFE(IRQ_STACK)   ; End of IRQ_STACK

;---------------------------------------------------------------
; Initialize C (SYS & USR) pointer
;---------------------------------------------------------------
  bic     r0, r0, #MODE_BITS                ; Clear the mode bits
  orr     r0, r0, #SYS_MODE                 ; Set System mode bits
  msr     cpsr_c, r0                        ; Change the mode
  ldr     sp, =SFE(CSTACK)    ; End of CSTACK

;---------------------------------------------------------------
; Initilaize SVC stack pointer
;---------------------------------------------------------------
  bic   r0, r0, #MODE_BITS                  ; Clear the mode bits
  orr   r0, r0, #SVC_MODE                   ; Set System mode bits
  msr   cpsr_c, r0                          ; Change the mode
  ldr   sp, =SFE(SVC_STACK)     ; End of CSTACK

  bx    lr


;---------------------------------------------------------------
; Static Memory Controller
;---------------------------------------------------------------
BANK0 equ 0x30002400
;---------------------------------------------------------------
SMC_Init:
;---------------------------------------------------------------

    LDR     r1, =0x1F3D;
    LDR     r0, =BANK0;
    STR     r1, [r0, #0];
    bx  lr


;---------------------------------------------------------------
; Dynamic Memory Controller
;---------------------------------------------------------------
DMC_BASE            equ   0x30002800
DMC_MB1Config       equ   (DMC_BASE + 0x00)
DMC_MB2Config       equ   (DMC_BASE + 0x04)
DMC_MB3Config       equ   (DMC_BASE + 0x08)
DMC_MB4Config       equ   (DMC_BASE + 0x0C)
DMC_MemConfig       equ   (DMC_BASE + 0x30)
DMC_SDRAM1ConfigLo  equ   (DMC_BASE + 0x10)
DMC_SDRAM1ConfigHi  equ   (DMC_BASE + 0x14)
DMC_SDRAM2ConfigLo  equ   (DMC_BASE + 0x18)
DMC_SDRAM2ConfigHi  equ   (DMC_BASE + 0x1C)
DMC_SDRAM3ConfigLo  equ   (DMC_BASE + 0x20)
DMC_SDRAM3ConfigHi  equ   (DMC_BASE + 0x24)
DMC_SDRAM4ConfigLo  equ   (DMC_BASE + 0x28)
DMC_SDRAM4ConfigHi  equ   (DMC_BASE + 0x2C)
DMC_Size1           equ   (DMC_BASE + 0x034)
DMC_StepSize        equ   0x0200
;---------------------------------------------------------------
; SDRAM config
;---------------------------------------------------------------
DMC_8bitCol         equ 0x0000 ;8bit column width
DMC_9bitCol         equ 0x0001 ;9bit column width
DMC_10bitCol        equ 0x0002 ;10bit column width
DMC_IdleTimeU       equ 0x0004 ;(Field Base) Minimum cycles the memdrv must spend in idle state
DMC_SetupTimeU      equ 0x0020 ;(Field Base) Number of cycles spent in decoding state
DMC_DataLatU        equ 0x0100 ;(Field Base) Number of cycles between memory access and data available
DMC_16bitDev        equ 0x0400 ;External Memory Device width: 16 bit
DMC_RefrU           equ 0x0001 ;(Field Base) Refresh period (usecs)
DMC_Bank0ON         equ 0x0100 ;Bank0 on
DMC_Bank1ON         equ 0x0200 ;Bank1 on
DMC_Bank2ON         equ 0x0400 ;Bank2 on
DMC_Bank3ON         equ 0x0800 ;Bank3 on
DMC_SDRAMType       equ 0x1000 ;SDRAM type
DMC_PSnormal        equ 0x0000 ; Normal mode Power Save
;DMC_MB1Config_value equ   0x0624
;DMC_MemConfig_value equ   0x1104


;---------------------------------------------------------------
SDRAM_Init:
;---------------------------------------------------------------

    LDR     r1, =((32768 / DMC_StepSize) - 1);
    LDR     r0, =DMC_Size1;
    STR     r1, [r0, #0];

    LDR     r0, =DMC_MB1Config;
    LDR     r1, =(DMC_16bitDev + 2 * DMC_DataLatU + 1 * DMC_SetupTimeU + 1 * DMC_IdleTimeU + DMC_9bitCol);
    STR     r1, [r0, #0];

    LDR     r0, =DMC_MemConfig;
    LDR     r1, =(DMC_PSnormal + DMC_SDRAMType + DMC_Bank0ON + 4 * DMC_RefrU);
    STR     r1, [r0, #0];

    LDR     r0, =DMC_SDRAM1ConfigLo;
    LDR     r1, =DMC_SDRAM1ConfigHi;

;precharge all banks
    LDR         r2, =0x3FFF;
    STR         r2, [r0, #0];
    LDR         r2, =0x0005;
    STR         r2, [r1, #0] ;
    nop;
    nop;

;self refresh 1 cycle
    LDR         r2, =0x0000;
    STR         r2, [r0, #0];
    LDR         r2, =0x0003 ;
    STR         r2, [r1, #0];
    nop;
    nop;

;self refresh 2 cycle
    LDR         r2, =0x0000 ;
    STR         r2, [r0, #0];
    LDR         r2, =0x0003 ;
    STR         r2, [r1, #0];
    nop;
    nop;

;MR prog
    LDR         r2, =0x0023 ;
    STR         r2, [r0, #0];
    LDR         r2, =0x0007 ;
    STR         r2, [r1, #0];

    bx    lr



;---------------------------------------------------------------
  END