hal_map.h

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//-----------------------------------------------------------------------------
// HAL_MAP FOR SpearNet
//-----------------------------------------------------------------------------
// DATE:     19/06/05
// REVISION: 1.5
//
// History:
// rev 1.5  - DMC_TypeDef structure updated, VJ
//-----------------------------------------------------------------------------
#ifndef HAL_MAP_H
#define HAL_MAP_H

//-----------------------------------------------------------------------------
#include "hal_type.h"

//-----------------------------------------------------------------------------
// Clock
//-----------------------------------------------------------------------------
#define FREG_OSC (u32)(25000000)

#define FD   (u32)48   /* Feedback Divider */
#define PRE  (u32)25   /* Pre Divider */
#define POST (u32)1    /* Post Divider */
//SYSCLK = ((u32)2 * FD * FREG_OSC) / PRE / ((u32)2<<POST)
#define SYSCLK (u32)(48000000)

//-----------------------------------------------------------------------------
// SpearNet BASE ADDRESSES
//-----------------------------------------------------------------------------
#define APB_BASE        0x30000000           /* APB bridge Base Address */
#define IC_BASE         (APB_BASE + 0x0000)  /* Interrupt Controller */
#define GPT_BASE        (APB_BASE + 0x0400)  /* General Purpose Timers */
#define WD_BASE         (APB_BASE + 0x0800)  /* Watch Dog Timers */
#define RTC_BASE        (APB_BASE + 0x0C00)  /* Real Time Clock */
#define GPIO_BASE       (APB_BASE + 0x1000)  /* General Purpose I/Os */
#define I2C_BASE        (APB_BASE + 0x1400)  /* I2C */
#define UART_BASE       (APB_BASE + 0x1800)  /* UART */
#define CR_BASE         (APB_BASE + 0x1C00)  /* Configuration Registers */
#define DMA_CGP_BASE    (APB_BASE + 0x2000)  /* DMA Controller General Purpose */
#define SMC_BASE        (APB_BASE + 0x2400)  /* Static Memory Controller */
#define DMC_BASE        (APB_BASE + 0x2800)  /* Dynamic Memory Controller */
#define USB_HC_BASE     (APB_BASE + 0x2C00)  /* USB Host Controller */
#define DMA_MAC_BASE    (APB_BASE + 0x3000)  /* DMA MAC */
#define MAC_EC_BASE     (APB_BASE + 0x3400)  /* MAC Ethernet Controller */

//-----------------------------------------------------------------------------
// Interrupt Controller (32bit registers)
//-----------------------------------------------------------------------------
typedef volatile struct
{
  vu32 CONTROL;            //(0000) RW
  vu32 IRQ_STATUS;         //(0004) RO
  vu32 FIQ_STATUS;         //(0008) RO
  vu32 PENDING;            //(000C) RO
  vu32 CONFIG_1;           //(0010) RW
  vu32 CONFIG_2;           //(0014) RW
  vu32 EMPTY1;             //(0018) RO
  vu32 EMPTY2;             //(001C) RO
  vu32 ENABLE;             //(0020) RW
  vu32 EMPTY3;             //(0024) RO
  vu32 EMPTY4;             //(0028) RO
  vu32 EMPTY5;             //(002C) RO
  vu32 SOFT_INTERRUPT;     //(0030) RW
} IC_TypeDef;

//-----------------------------------------------------------------------------
// General Purpose Timers (16bit registers, 32bit aligned)
//-----------------------------------------------------------------------------
typedef volatile struct
{
  vu32 CONTROL;            //(0000) RW
  vu32 STATUS_INT_ACK;     //(0004) RO for STATUS, RW for INT_ACK
  vu32 COMPARE;            //(0008) RW
  vu32 COUNT;              //(000C) RO
  vu32 COUNT_REDGE;        //(0010) RO
  vu32 COUNT_fEDGE;        //(0014) RO
} GPT_TypeDef;

//-----------------------------------------------------------------------------
// Watch Dog Timers (16bit registers, 32bit aligned)
//-----------------------------------------------------------------------------
typedef volatile struct
{
  vu32 CONTROL;            //(0000) RW
  vu32 STATUS;             //(0004) RO
  vu32 MAX_CNT;            //(0008) RW
  vu32 COUNTER;            //(000C) RO
} WD_TypeDef;

//-----------------------------------------------------------------------------
// Real Time Clock
//-----------------------------------------------------------------------------
typedef volatile struct
{
  vu32 TIME;               //(0000) RW
  vu32 DATE;               //(0004) RW
  vu32 ALARM_TIME;         //(0008) RW
  vu32 ALARM_DATE;         //(000C) RW
  vu32 CONTROL;            //(0010) RW
  vu32 STATUS;             //(0014) RO
} RTC_TypeDef;

//-----------------------------------------------------------------------------
// GPIO (8bit registers)
//-----------------------------------------------------------------------------
typedef volatile struct
{
  vu8  DIR;                //(0000) RW
  vu8  EMPTY1[3];          //(0001..0003)
  vu8  DIN;                //(0004) RO
  vu8  EMPTY2[11];         //(0005..000F)
  vu8  DOUT0;              //(0010) WO
  vu8  EMPTY3[3];          //(0011..0013)
  vu8  DOUT1;              //(0014) WO
  vu8  EMPTY4[3];          //(0015..0017)
  vu8  DOUT2;              //(0018) WO
  vu8  EMPTY5[3];          //(0019..001B)
  vu8  DOUT3;              //(001C) WO
  vu8  EMPTY6[3];          //(001D..001F)
  vu8  DOUT4;              //(0020) WO
  vu8  EMPTY7[3];          //(0021..0023)
  vu8  DOUT5;              //(0024)WO
} GPIO_TypeDef;

//-----------------------------------------------------------------------------
// I2C (8bit registers, 32bit aligned)
//-----------------------------------------------------------------------------
typedef volatile struct
{
  vu32  CR;                //(0000) RW
  vu32  SR1;               //(0004) RW
  vu32  SR2;               //(0008) RW
  vu32  CCR;               //(000C) RW
  vu32  OAR;               //(0010) RW
  vu32  EMPTY1;            //(0014) RO
  vu32  DR;                //(0018) RW
} I2C_TypeDef;

//-----------------------------------------------------------------------------
// UART (16bit registers)
//-----------------------------------------------------------------------------
typedef volatile struct
{
  vu16 BRR;                //(0000) RW Baud Rate Register
  vu16 EMPTY1;             //(0002)
  vu16 TBR;                //(0004) WO Transmit Buffer Register
  vu16 EMPTY2;             //(0006)
  vu16 RBR;                //(0008) RO Receive Buffer Register
  vu16 EMPTY3;             //(000A)
  vu16 CR;                 //(000C) RW Control Register
  vu16 EMPTY4;             //(000E)
  vu16 IER;                //(0010) RW Interrrut Enable Register
  vu16 EMPTY5;             //(0012)
  vu16 SR;                 //(0014) RO Status Register
  vu16 EMPTY6;             //(0016)
  vu16 GTR;                //(0018) RW Guard Time Register
  vu16 EMPTY7;             //(001A)
  vu16 TOR;                //(001C) RW Time Out Register
  vu16 EMPTY8;             //(001E)
  vu16 TRR;                //(0020) WO Transmit Reset Register
  vu16 EMPTY9;             //(0022)
  vu16 RRR;                //(0024) WO Receive Reset Register
} UART_TypeDef;

//-----------------------------------------------------------------------------
// Configuration Registers (8bit registers, 32bit aligned)
//-----------------------------------------------------------------------------
typedef volatile struct
{
  vu32 FW_CFG;             //(0000)
  vu32 HW_CFG;             //(0004)
  vu32 GLOBAL_CONTROL;     //(0008)
  vu32 GLOBAL_STATUS;      //(000C)
  vu32 SHRAM_TEST_CTRL;    //(0010)
  vu32 SHRAM_TEST_STATUS;  //(0014)
} CR_TypeDef;

//-----------------------------------------------------------------------------
// DMA Controller General Purpose (16bit registers, 32bit aligned)
//-----------------------------------------------------------------------------
// DMA channels CH0, CH1, CH2 and CH3
typedef volatile struct
{
  vu32 DMASourceLow;       //(0000) RW
  vu32 DMASourceHigh;      //(0004) RW
  vu32 DMADestLo;          //(0008) RW
  vu32 DMADestHigh;        //(000C) RW
  vu32 DMAMax;             //(0010) RW
  vu32 DMACtrl;            //(0014) RW
  vu32 DMASoCurrLo;        //(0018) RO
  vu32 DMASoCurrHigh;      //(001C) RO
  vu32 DMADeCurrLo;        //(0020) RO
  vu32 DMADeCurrHigh;      //(0024) RO
  vu32 DMATCnt;            //(0028) RO
} DMA_TypeDef;

// DMA Mask & Clear & Status
typedef volatile struct
{
  vu32 DMAMask;            //(0000) RW
  vu32 DMAClr;             //(0004) RW