hal_map.h
来自「最新版IAR FOR ARM（EWARM）5.11中的代码例子」· C头文件 代码 · 共 401 行 · 第 1/2 页
H
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vu32 DMAStatus; //(0008) RW
} DMA_CH_TypeDef;
//-----------------------------------------------------------------------------
// Static Memory Controller (16bit registers)
//-----------------------------------------------------------------------------
typedef volatile struct
{
vu16 REG0; //(0000) RW
vu16 EMPTY1; //(0002)
vu16 REG1; //(0004) RW
vu16 EMPTY2; //(0006)
vu16 REG2; //(0008) RW
vu16 EMPTY3; //(000A)
vu16 REG3; //(000C) RW
} SMC_TypeDef;
//-----------------------------------------------------------------------------
// Dynamic Memory Controller (16bit registers)
//-----------------------------------------------------------------------------
typedef volatile struct
{
vu16 MB1Config; //(0000) RW
vu16 EMPTY1; //(0002)
vu16 MB2Config; //(0004) RW
vu16 EMPTY2; //(0006)
vu16 MB3Config; //(0008) RW
vu16 EMPTY3; //(000A)
vu16 MB4Config; //(000C) RW
vu16 EMPTY4; //(000E)
vu16 SDRAM1ConfigLo; //(0010) RO
vu16 EMPTY5; //(0012)
vu16 SDRAM1ConfigHi; //(0014) RO
vu16 EMPTY6; //(0006)
vu16 SDRAM2ConfigLo; //(0018) RO
vu16 EMPTY7; //(001A)
vu16 SDRAM2ConfigHi; //(001C) RO
vu16 EMPTY8; //(001E)
vu16 SDRAM3ConfigLo; //(0020) RO
vu16 EMPTY9; //(0022)
vu16 SDRAM3ConfigHi; //(0024) RO
vu16 EMPTY10; //(0026)
vu16 SDRAM4ConfigLo; //(0028) RO
vu16 EMPTY11; //(002A)
vu16 SDRAM4ConfigHi; //(002C) RO
vu16 EMPTY12; //(002E)
vu16 MemConfig; //(0030) RW
vu16 EMPTY13; //(0032)
vu16 Bank0Size; //(0034) RW
vu16 EMPTY14; //(0036)
vu16 Bank1Size; //(0038) RW
vu16 EMPTY15; //(003A)
vu16 Bank2Size; //(003C) RW
vu16 EMPTY16; //(003E)
vu16 Bank3Size; //(0040) RW
} DMC_TypeDef;
//-----------------------------------------------------------------------------
// USB Host Controller (32bit registers)
//-----------------------------------------------------------------------------
#define NDP 1
typedef volatile struct
{
vu32 HcRevision; //(0000) Revision field (Read only)
vu32 HcControl; //(0004) USB Host Controller Operating mode
vu32 HcCommandStatus; //(0008) Used by the Host Controller to receive commands issused by the Host Controller Driver
vu32 HcInterruptStatus; //(000C) Register provides status on various events that cause hardware interrupts
vu32 HcInterruptEnable; //(0010) Register is used to control which events generate a hardware interrupt
vu32 HcInterruptDisable; //(0014) To clear the corresponding bit in the HcInterruptEnable register
vu32 HcHCCA; //(0018) Register contains the physical address of the Host Controller Communication Area
vu32 HcPeriodCurrentED; //(001C) Register contains the physical address of the current isochronous or Interrupt Endpoint Descriptor
vu32 HcControlHeadED; //(0020) Register contains the physical address of the first Endpoint Descriptor of the Control list
vu32 HcControlCurrentED; //(0024) Register contains the physical address of the current Endpont Descriptor of the control list
vu32 HcBulkHeadED; //(0028) Register contains the physical address of the first Endpoint Descriptor of the Bulk list
vu32 HcBulkCurrentED; //(002C) Register contains the physical address of the current endpoint of the Bulk list. As the bulk list will be served in a round-robin fashion, the endpoints will be ordered according to their insertion to the list.
vu32 HcDoneHead; //(0030) Contains the physical address of the last completed transfer descriptor that was added to the Done queue.
vu32 HcFmInterval; //(0034) Register contains a 14-bit value which indicates the bit time interval in a frame, and a 15-bit value indicating the full speed maximum packet size that the host controller may carry out.
vu32 HcFmRemaining; //(0038) Register is a 14-bit down counter showing the bit time remaining in the current frame
vu32 HcFmNumber; //(003C) Register is a 16-bit counter providein a reference among events happening in the host controller and the host controller driver
vu32 HcPeriodicStart; //(0040) Register has a 14-bit programmable value which determines when is the earliest time HC should start processing the periodic list.
vu32 cLSThreshold; //(0044) Register contains an 11-bit value used by the host controller to determine whether to commit to the transfer of a maximum of 8-byte LS packet before EOF.
vu32 HcRhDescriptorA; //(0048) Register (first of 2) describes the characteristics of the root hub
vu32 HcRhDescriptorB; //(004C) Register (second of 2) describes the characteristic of the root hub
vu32 HcRhStatus; //(0050) Register represents the Hub status field (lower word of Dword) and the Hub Status Change field (upper word of Dword)
vu32 HcRhPortStatus[NDP];//(0054) [1:NDP] is used to control and report port events on a per-port basis.
} USB_TypeDef;
//-----------------------------------------------------------------------------
// DMA MAC (32bit registers)
//-----------------------------------------------------------------------------
typedef volatile struct
{
vu32 DMA_STS_CNTL; //(0000) Ethernet DMA, status and control register
vu32 DMA_INT_EN; //(0004) Ethernet DMA, Interrupt sources enable register
vu32 DMA_INT_STS; //(0008) Ethernet DMA, Interrupt status register
vu32 EMPTY1; //(000C)
vu32 RX_DMA_START; //(0010) Ethernet DMA, RX start register
vu32 RX_DMA_CNTL; //(0014) Ethernet DMA, RX control register
vu32 RX_DMA_ADDR; //(0018) Ethernet DMA, RX base address register
vu32 RX_DMA_NXT; //(001C) Ethernet DMA, RX next descriptor address register
vu32 RX_DMA_CADDR; //(0020) Ethernet DMA, RX current address register
vu32 RX_DMA_CXFER; //(0024) Ethernet DMA, RX current transfer count register
vu32 RX_DMA_TO; //(0028) Ethernet DMA, RX time out register
vu32 RX_DMA_FIFO; //(002C) Ethernet DMA, RX FIFO status register
vu32 TX_DMA_START; //(0030) Ethernet DMA, TX start register
vu32 TX_DMA_CNTL; //(0034) Ethernet DMA, TX control register
vu32 TX_DMA_ADDR; //(0038) Ethernet DMA, TX base address register
vu32 TX_DMA_NXT; //(003C) Ethernet DMA, TX next descriptor address register
vu32 TX_DMA_CADDR; //(0040) Ethernet DMA, TX current address register
vu32 TX_DMA_CXFER; //(0044) Ethernet DMA, TX current transfer count register
vu32 TX_DMA_TO; //(0048) Ethernet DMA, TX time out register
vu32 TX_DMA_FIFO; //(004C) Ethernet DMA, TX FIFO status register
vu8 EMPTY2[176]; //(0050..00FF), (0xFF-0x50) = 175
vu32 RX_FIFO[32]; //(0100..017C), RX local FIFO, 128/4 = 32
vu8 EMPTY3[128]; //(0180..01FF), (0x1FF-0x180) = 127
vu32 TX_FIFO[32]; //(0200..027C), TX local FIFO, 128/4 = 32
} DMA_MAC_TypeDef;
//-----------------------------------------------------------------------------
// MAC Ethernet Controller (32bit registers)
//-----------------------------------------------------------------------------
typedef volatile struct
{
vu32 MAC_CNTL; //(0000) MAC control register
vu32 MAC_ADDH; //(0004) MAC address high register
vu32 MAC_ADDL; //(0008) MAC address low register
vu32 MAC_MCHTH; //(000C) MAC, multi cast hash table high register
vu32 MAC_MCHTL; //(0010) MAC, multi cast hash table low register
vu32 MII_ADDR; //(0014) MII, address register
vu32 MII_DATA; //(0018) MII, data register
vu32 FCR; //(001C) Flow control register
vu32 VLAN1; //(0020) VLAN1 tag register
vu32 VLAN2; //(0024) VLAN2 tag register
vu8 EMPTY1[216]; //(0028..0FF), (0xFF-0x28) = 215
vu32 MMC_CTRL_REG; //(0100) MMC Statistic Control Register
vu32 MMC_INT_HI_REG; //(0104) MMC Statistic Interrupt High Register
vu32 MMC_INT_LO_REG; //(0108) MMC Statistic Interrupt Low Register
vu32 MMC_INT_MSK_HI_REG; //(010C) MMC Statistic Interrupt Mask High Register
vu32 MMC_INT_MSK_LO_REG; //(0110) MMC Statistic Interrupt Mask Low Register
vu8 EMPTY2[236]; //(0114..1FF), (0x1FF-0x114) = 235
vu32 RxNumFrmsAllCntr; //(0200) All frames received counter. This includes good and bad frames. Counter is incremented each time a frame is received.
vu32 RxNumFrmsOkCntr; //(0204) Good frame received counter. This includes good frames only, which are free from runt frame error, frame too long error, collision error, MII error, dribble bit error, CRC error, invalid length error and FIFO overflow error.
vu32 RxCntrlFrmsCntr; //(0208) Control frames received counter. This includes control frames, which are free from runt frame error, frame too long error, collision error, MII error, dribble bit error, CRC error, invalid length error and FIFO overflow error.
vu32 RxUnsupCntrlCntr; //(020C) Unsupported control frames received counter. This includes control frames, which are free from runt frame error, frame too long error, collision error, MII error, dribble bit error, CRC error, invalid length error and FIFO overflow error but whose length/type field is not supported.
vu32 RxNumBytsAllCntr; //(0210) No of bytes received counter. This includes all frames frame length added. Excludes preamble.
vu32 RxNumBytsOkCntrr; //(0214) No of bytes received counter. This includes all frames frame length added which are free from runt frame error, frame too long error, collision error, MII error, dribble bit error, CRC error, invalid length error and FIFO overflow error.
vu32 RxLenEqual64Cntr; //(0218) Frame with length equal to 64 bytes counter. Includes good and bad frames.
vu8 EMPTY3[236]; //(021C..0307), (0x307-0x21C) = 235
vu32 TxNumBytsAllCntr; //(0308) Total number of transmitted bytes counter. Counter is incremented each time transmit status is received. Includes good and bad frames but no retries.
vu32 TxNumBytsOkCntr; //(030C) Total number of (well) transmitted bytes counter. Counter for bytes of a good frame transmitted. Does not include retries. The good frames are the ones for which the frame abort and packet retry bits in transmit status are reset.
vu32 TxLenEqual64Cntr; //(0310) Frames with length equal to 64 counter. Counter for frames with length equal to 64. Includes good and bad frames but no retries.
vu32 TxLen65_127Cntr; //(0314) Frames with length from 65 to 127 counter. Counter for frames with length between 65 and 127 bytes. Includes good and bad frames but no retries.
vu32 TxLen128_255Cntr; //(0318) Frames with length from 128 to 255 counter. Counter for frames with length between 128 and 255 bytes. Includes good and bad frames but no retries.
vu32 TxLen256_511Cntr; //(031C) Frames with length from 256 to 511 counter. Counter for frames with length between 256 and 511 bytes. Includes good and bad frames but no retries.
vu32 TxLen512_1023Cntr; //(0320) Frames with length from 512 to 1023 counter. Counter for frames with length between 512 and 1023 bytes. Includes good and bad frames but no retries.
vu32 TxLen1024_MaxCntr; //(0324) Frames with length from 1024 to MaxPktSize counter. Counter for frames with length between 1024 and maximum frame lenght bytes. Includes good and bad frames but no retries.
vu32 TxUnicastCntr; //(0328) No of Unicast frames transmitted counter. Includes good frames only, no retries.
vu32 TxMulticastCntr; //(032C) No of multicast frames transmitted counter. Includes good frames only, no retries.
vu32 TxBroadcastCntr; //(0330) No of broadcast frames transmitted counter. Includes good frames only, no retries.
vu32 TxFifoUndFloCntr; //(0334) No of frames aborted due to FIFO error counter. This counter is incremented when the under run bit in transmit status is set.
vu32 TxNumBadFrmsCntr; //(0338) No of frames aborted counter. This counter is incremented if either the frame aborted or the heart bit fail are set in transmit status.
vu32 TxSingleColCntr; //(033C) No of frames with single collision counter. The counter is incremented when the collisions count = 1 and packet retry set in transmit status.
vu32 TxMultiColCntr; //(0340) No of frames with multiple collisions counter. The counter is incremented when the collisions count > 1 and packet retry set in transmit status.
vu32 TxNumDeffredCntr; //(0344) No of frames deferred counter. This counter is incremented when the deferred bit in transmit status is set.
vu32 TxLateColCntr; //(0348) No of frames with late collision counter. This counter is incremented when the late collision bit in transmit status is set.
vu32 TxAbortedFrmsCntr; //(034C) No of frames aborted counter. This counter is incremented when the frame aborted bit in transmit status is set.
vu32 TxNoCrsCntr; //(0350) Number of frames with no carrier counter. This counter is incremented when either the no carrier or the loss of carrier bit in transmit status is set.
vu32 TxXsDeferalCntr; //(0354) No of frames with excessive deferral counter. This counter is incremented when the excessive deferral bit in transmit status is set.
} MAC_EC_TypeDef;
//-----------------------------------------------------------------------------
// POINTERS
//-----------------------------------------------------------------------------
#define IC ((IC_TypeDef*) IC_BASE)
#define GPT1 ((GPT_TypeDef*) (GPT_BASE+0x0080))
#define GPT2 ((GPT_TypeDef*) (GPT_BASE+0x0100))
#define WD ((WD_TypeDef*) WD_BASE)
#define RTC ((RTC_TypeDef*) RTC_BASE)
#define GPIO ((GPIO_TypeDef*) GPIO_BASE)
#define I2C ((I2C_TypeDef*) (I2C_BASE+0x0160))
#define UART ((UART_TypeDef*) UART_BASE)
#define CONFR ((CR_TypeDef*) CR_BASE)
#define DMA_CH0 ((DMA_TypeDef*) (DMA_CGP_BASE+0x0000))
#define DMA_CH1 ((DMA_TypeDef*) (DMA_CGP_BASE+0x0040))
#define DMA_CH2 ((DMA_TypeDef*) (DMA_CGP_BASE+0x0080))
#define DMA_CH3 ((DMA_TypeDef*) (DMA_CGP_BASE+0x00C0))
#define DMA_CH ((DMA_CH_TypeDef*) (DMA_CGP_BASE+0x00F0))
#define SMC ((SMC_TypeDef*) SMC_BASE)
#define DMC ((DMC_TypeDef*) DMC_BASE)
#define USB ((USB_TypeDef*) USB_HC_BASE)
#define DMA_MAC ((DMA_MAC_TypeDef*) DMA_MAC_BASE)
#define MAC ((MAC_EC_TypeDef*) MAC_EC_BASE)
//-----------------------------------------------------------------------------
// END
//-----------------------------------------------------------------------------
#endif
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