📄 rtosinit_str75x.c
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/*********************************************************************
*
* IAR PowerPac - RTOS
*
* (c) Copyright IAR Systems 2006. All rights reserved.
*
**********************************************************************
----------------------------------------------------------------------
File : RTOSInit_STR75x.c (for ST STR75x CPUs)
Purpose : Initializes and handles the hardware for the OS as far
as required by the OS.
Feel free to modify this file acc. to your
target system.
-------- END-OF-HEADER ---------------------------------------------
*/
#include "RTOS.H"
#include "bsp.h"
#include "OS_Config.H"
/*********************************************************************
*
* Configuration
*
*********************************************************************/
/*********************************************************************
*
* Clock frequency settings
*/
#ifndef OS_FSYS /* CPU main clock frequency */
#define OS_FSYS 48000000L /* may depend on PLL */
#endif
#ifndef OS_PCLK_TIMER /* Peripheral clock for timer */
#define OS_PCLK_TIMER OS_FSYS/OS_TIMCLK_DIVIDER
/* May vary from CPU clock */
#endif /* depending on CPU */
#ifndef OS_PCLK_UART /* Peripheral clock for UART */
#define OS_PCLK_UART OS_FSYS/(OS_TIMCLK_DIVIDER * OS_PCLK_DIVIDER * _TIM_PESCALER)
/* May vary from CPU clock */
#endif /* depending on CPU */
#ifndef OS_INIT_PLL /* PLL may be initialized */
#define OS_INIT_PLL 1 /* during startup */
#endif
#define _OS_TIMER_INTERVAL (OS_PCLK_TIMER / TICK_PER_SEC)
/*********************************************************************
*
* UART settings for OSView
* If you do not want (or can not due to hardware limitations)
* to dedicate a UART to OSView, please define it to be -1
* Currently the standard code enables UART 0 per default
* and supports UART0 to UART3
*/
#ifndef OS_UART
#define OS_UART 0
#endif
#ifndef OS_BAUDRATE
#define OS_BAUDRATE 38400L
#endif
/****** Define behavior of undefined interrupt handling ************/
#ifndef OS_IGNORE_UNDEFINED_INTERRUPT
#define OS_IGNORE_UNDEFINED_INTERRUPT 0
#endif
/****** End of configuration settings *******************************/
#define OS_UART_USED ((OS_UART == 0) || (OS_UART == 1) || (OS_UART == 2))
/*********************************************************************
*
* Local defines (sfrs used in RTOSInit.c)
*
**********************************************************************
*/
/****** UART sfdr definition ****************************************/
/****** UART0 *******************************************************/
#define __UART0_BASE 0xFFFFD400
#define __UART1_BASE 0xFFFFD800
#define __UART2_BASE 0xFFFFDC00
#define __UART_DR_OFFS 0x00
#define __UART_RSR_OFFS 0x04
#define __UART_FR_OFFS 0x18
#define __UART_BRKR_OFFS 0x1C
#define __UART_IBRDR_OFFS 0x24
#define __UART_FBRDR_OFFS 0x28
#define __UART_LCR_OFFS 0x2C
#define __UART_CR_OFFS 0x30
#define __UART_IFLSR_OFFS 0x34
#define __UART_IMSCR_OFFS 0x38
#define __UART_RISR_OFFS 0x3C
#define __UART_MISR_OFFS 0x40
#define __UART_ICR_OFFS 0x44
#define __UART_DMACR_OFFS 0x48
/****** Assign UART sfrs used for OSView communication ***********/
#if OS_UART_USED
#if (OS_UART == 0)
#define _OS_UART_BASE __UART0_BASE
#define _OS_UART_ID UART0_VECT_ID
#define _UART_RX_PIN (0x00000001<<10)
#define _UART_TX_PIN (0x00000001<<11)
#elif (OS_UART == 1)
#define _OS_UART_BASE __UART1_BASE
#define _OS_UART_ID UART1_VECT_ID
#define _UART_RX_PIN (0x00000001<<20)
#define _UART_TX_PIN (0x00000001<<21)
#elif (OS_UART == 2)
#define _OS_UART_BASE __UART2_BASE
#define _OS_UART_ID UART2_VECT_ID
#define _UART_RX_PIN (0x00000001<<24)
#define _UART_TX_PIN (0x00000001<<25)
#endif
#define _OS_UART_DR *(volatile OS_U16*)(_OS_UART_BASE + __UART_DR_OFFS)
#define _OS_UART_RxBUFR _OS_UART_DR
#define _OS_UART_TxBUFR _OS_UART_DR
#define _OS_UART_RSR *(volatile OS_U16*)(_OS_UART_BASE + __UART_RSR_OFFS)
#define _OS_UART_FR *(volatile OS_U16*)(_OS_UART_BASE + __UART_FR_OFFS)
#define _OS_UART_BRKR *(volatile OS_U16*)(_OS_UART_BASE + __UART_BRKR_OFFS)
#define _OS_UART_IBRDR *(volatile OS_U16*)(_OS_UART_BASE + __UART_IBRDR_OFFS)
#define _OS_UART_FBRDR *(volatile OS_U16*)(_OS_UART_BASE + __UART_FBRDR_OFFS)
#define _OS_UART_LCR *(volatile OS_U16*)(_OS_UART_BASE + __UART_LCR_OFFS)
#define _OS_UART_CR *(volatile OS_U16*)(_OS_UART_BASE + __UART_CR_OFFS)
#define _OS_UART_IFLSR *(volatile OS_U16*)(_OS_UART_BASE + __UART_IFLSR_OFFS)
#define _OS_UART_IMSCR *(volatile OS_U16*)(_OS_UART_BASE + __UART_IMSCR_OFFS)
#define _OS_UART_RISR *(volatile OS_U16*)(_OS_UART_BASE + __UART_RISR_OFFS)
#define _OS_UART_MISR *(volatile OS_U16*)(_OS_UART_BASE + __UART_MISR_OFFS)
#define _OS_UART_ICR *(volatile OS_U16*)(_OS_UART_BASE + __UART_ICR_OFFS)
#define _OS_UART_DMACR *(volatile OS_U16*)(_OS_UART_BASE + __UART_DMACR_OFFS)
#define _UART_RX_ERROR_FLAGS (0x0F00) // Parity, framing, overrun error
#define _UART_DATA_MASK (0x00FF)
#define _OS_UART_PRIO 0x01 // lowest priority for OS UART interrupts
#define _TX_INTR (1UL<<5)
#define _RX_INTR ((1UL<<4) | (1UL<<6) | (1UL<<7) | (1UL<<8) | (1UL<<9) | (1UL<<10))
#endif
/****** GPIO register ***********************************************/
#define __IOPORT_BASE 0xFFFFE400
#define __GPIO0_PC0 *(volatile OS_U32*)(__IOPORT_BASE + 0x00)
#define __GPIO0_PC1 *(volatile OS_U32*)(__IOPORT_BASE + 0x04)
#define __GPIO0_PC2 *(volatile OS_U32*)(__IOPORT_BASE + 0x08)
#define __GPIO0_PD *(volatile OS_U32*)(__IOPORT_BASE + 0x0C)
#define __GPIO0_PM *(volatile OS_U32*)(__IOPORT_BASE + 0x10)
#define __GPIO0_REMAP0 *(volatile OS_U32*)(__IOPORT_BASE + 0x20)
#define __GPIO0_REMAP1 *(volatile OS_U32*)(__IOPORT_BASE + 0x24)
#define __GPIO1_PC0 *(volatile OS_U32*)(__IOPORT_BASE + 0x40)
#define __GPIO1_PC1 *(volatile OS_U32*)(__IOPORT_BASE + 0x44)
#define __GPIO1_PC2 *(volatile OS_U32*)(__IOPORT_BASE + 0x48)
#define __GPIO1_PD *(volatile OS_U32*)(__IOPORT_BASE + 0x4C)
#define __GPIO1_PM *(volatile OS_U32*)(__IOPORT_BASE + 0x50)
#define __GPIO2_PC0 *(volatile OS_U32*)(__IOPORT_BASE + 0x80)
#define __GPIO2_PC1 *(volatile OS_U32*)(__IOPORT_BASE + 0x84)
#define __GPIO2_PC2 *(volatile OS_U32*)(__IOPORT_BASE + 0x88)
#define __GPIO2_PD *(volatile OS_U32*)(__IOPORT_BASE + 0x8C)
#define __GPIO2_PM *(volatile OS_U32*)(__IOPORT_BASE + 0x90)
/****** Power, reset clock control unit register ********************/
#define __MRCC_BASE 0x60000020
#define __MRCC_CLKCTL *(volatile OS_U32*)(__MRCC_BASE + 0x00)
#define __MRCC_RFSR *(volatile OS_U32*)(__MRCC_BASE + 0x04)
#define __MRCC_PWRCTRL *(volatile OS_U32*)(__MRCC_BASE + 0x08)
#define __MRCC_PCLKEN *(volatile OS_U32*)(__MRCC_BASE + 0x10)
#define __MRCC_PSWRES *(volatile OS_U32*)(__MRCC_BASE + 0x14)
#define __MRCC_BKP0 *(volatile OS_U32*)(__MRCC_BASE + 0x20)
#define __MRCC_BKP1 *(volatile OS_U32*)(__MRCC_BASE + 0x24)
#define __CFG_GLCONF *(volatile OS_U32*)(0x60000000 + 0x10)
/****** Timer sfr definition ****************************************/
#define __TB_BASE 0xFFFF8800
#define __TB_CR_OFFS 0x00
#define __TB_SCR_OFFS 0x04
#define __TB_IMCR_OFFS 0x08
#define __TB_RSR_OFFS 0x18
#define __TB_RER_OFFS 0x1C
#define __TB_ISR_OFFS 0x20
#define __TB_CNT_OFFS 0x24
#define __TB_PSC_OFFS 0x28
#define __TB_ARR_OFFS 0x30
#define __TB_ICR1_OFFS 0x4C
/****** Assign timer sfrs used for OS timer *************************/
/****** initially, we use timebase timer *************************/
#define _OS_TIM_BASE __TB_BASE
#define _OS_TIM_CR *(volatile OS_U16*)(_OS_TIM_BASE + __TB_CR_OFFS)
#define _OS_TIM_SCR *(volatile OS_U16*)(_OS_TIM_BASE + __TB_SCR_OFFS)
#define _OS_TIM_IMCR *(volatile OS_U16*)(_OS_TIM_BASE + __TB_IMCR_OFFS)
#define _OS_TIM_RSR *(volatile OS_U16*)(_OS_TIM_BASE + __TB_RSR_OFFS)
#define _OS_TIM_RER *(volatile OS_U16*)(_OS_TIM_BASE + __TB_RER_OFFS)
#define _OS_TIM_ISR *(volatile OS_U16*)(_OS_TIM_BASE + __TB_ISR_OFFS)
#define _OS_TIM_CNT *(volatile OS_U16*)(_OS_TIM_BASE + __TB_CNT_OFFS)
#define _OS_TIM_PSC *(volatile OS_U16*)(_OS_TIM_BASE + __TB_PSC_OFFS)
#define _OS_TIM_ARR *(volatile OS_U16*)(_OS_TIM_BASE + __TB_ARR_OFFS)
#define _OS_TIM_ICR1 *(volatile OS_U16*)(_OS_TIM_BASE + __TB_ICR1_OFFS)
#define _TIMER_INT_BIT_NO 31
/****** Enhanced interrupt controller (EIC) *************************/
#define __EIC_BASE 0xFFFFF800
#define __EIC_ICR *(volatile OS_U32*)(__EIC_BASE + 0x00)
#define __EIC_CICR *(volatile OS_U32*)(__EIC_BASE + 0x04)
#define __EIC_CPIR *(volatile OS_U32*)(__EIC_BASE + 0x08)
#define __EIC_IVR *(volatile OS_U32*)(__EIC_BASE + 0x18)
#define __EIC_FIR *(volatile OS_U32*)(__EIC_BASE + 0x1C)
#define __EIC_IER *(volatile OS_U32*)(__EIC_BASE + 0x20)
#define __EIC_IPR *(volatile OS_U32*)(__EIC_BASE + 0x40)
#define __EIC_SIR0 *(volatile OS_U32*)(__EIC_BASE + 0x60)
#ifndef NUM_INT_SOURCES
#define NUM_INT_SOURCES 32
#endif
#define _INT_CHANNEL_MASK 0x0000001F
#define _INT_PRIORITY_MASK 0x0F
/*********************************************************************
*
* Static data
*
**********************************************************************
*/
static volatile OS_U32 _Dummy;
static OS_ISR_HANDLER* _apOS_ISRHandler[NUM_INT_SOURCES];
/*********************************************************************
*
* Local functions
*
**********************************************************************
*/
static void WriteLPBit(void);
/*********************************************************************
*
* OS_Tick interrupt Handler
*/
static void _OS_ISR_Tick(void) {
_OS_TIM_ISR = 0; // Clear OS timer interrupt flag
OS_HandleTick(); // Call OS tick handler
}
/*********************************************************************
*
* Global functions
*
**********************************************************************
*/
/*********************************************************************
*
* OS_InitPLL
*
* Function description
* Initialize main clock and PLL
* Should be called as early as possible in order to keep boot time short
* WARNING: Improper settings may lock CPU
* Please examine whether init sequence fits your hardware configuration
* We assume a CPU running with external 16MHz oscillator and switch to 48 MHz
*/
OS_INTERWORK void OS_InitPLL(void) {
// Flash init - disable burst
__CFG_GLCONF &=~(1UL << 8);
// select freeosc
__MRCC_CLKCTL &=~(1UL << 23);
// Disable PLL
__MRCC_CLKCTL &= ~(1UL << 24);
// Set clock dividers
// HCLK
__MRCC_CLKCTL &= ~(3UL << 3);
#if OS_HCLK_DIVIDER == 2
__MRCC_CLKCTL |= (1UL << 3);
#elif OS_HCLK_DIVIDER == 4
__MRCC_CLKCTL |= (2UL << 3);
#elif OS_HCLK_DIVIDER == 8
__MRCC_CLKCTL |= (3UL << 3);
#endif
// PCLK
__MRCC_CLKCTL &= ~(3UL << 0);
#if OS_PCLK_DIVIDER == 2
__MRCC_CLKCTL |= (1UL << 0);
#elif OS_PCLK_DIVIDER == 4
__MRCC_CLKCTL |= (2UL << 0);
#elif OS_PCLK_DIVIDER == 8
__MRCC_CLKCTL |= (3UL << 0);
#endif
// TIM clk
#if OS_PCLK_DIVIDER == 2
__MRCC_CLKCTL |= (1UL << 2);
#else
__MRCC_CLKCTL &= ~(1UL << 2);
#endif
// OSC 4/8 off
__MRCC_CLKCTL |= (1UL << 17);
}
/*********************************************************************
*
* OS_InitHW()
*
* Initialize the hardware (timer) required for the OS to run.
* May be modified, if an other timer should be used
*/
#define _OS_TIMER_ID TB_VECT_ID // Assign to TC1 global interrupt
#define _OS_TIMER_PRIO 0x01 // lowest priority
void OS_InitHW(void) {
OS_DI();
OS_InitPLL();
// Initialize Peripheral clock
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