📄 zd_chip.h
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/* Mandatory rates required in the BSS. When producing ACK or CTS messages, if * the device could not find an appropriate rate in CR_BASIC_RATE_TBL, it will * look for a rate in this table that is less than or equal to the rate of * the incoming frame. */#define CR_MANDATORY_RATE_TBL CTL_REG(0x0634)#define CR_RTS_CTS_RATE CTL_REG(0x0638)#define CR_WEP_PROTECT CTL_REG(0x063C)#define CR_RX_THRESHOLD CTL_REG(0x0640)/* register for controlling the LEDS */#define CR_LED CTL_REG(0x0644)/* masks for controlling LEDs */#define LED1 0x0100#define LED2 0x0200/* Seems to indicate that the configuration is over. */#define CR_AFTER_PNP CTL_REG(0x0648)#define CR_ACK_TIME_80211 CTL_REG(0x0658)#define CR_RX_OFFSET CTL_REG(0x065c)#define CR_PHY_DELAY CTL_REG(0x066C)#define CR_BCN_FIFO CTL_REG(0x0670)#define CR_SNIFFER_ON CTL_REG(0x0674)#define CR_ENCRYPTION_TYPE CTL_REG(0x0678)#define NO_WEP 0#define WEP64 1#define WEP128 5#define WEP256 6#define ENC_SNIFFER 8#define CR_ZD1211_RETRY_MAX CTL_REG(0x067C)#define CR_REG1 CTL_REG(0x0680)/* Setting the bit UNLOCK_PHY_REGS disallows the write access to physical * registers, so one could argue it is a LOCK bit. But calling it * LOCK_PHY_REGS makes it confusing. */#define UNLOCK_PHY_REGS 0x0080#define CR_DEVICE_STATE CTL_REG(0x0684)#define CR_UNDERRUN_CNT CTL_REG(0x0688)#define CR_RX_FILTER CTL_REG(0x068c)#define RX_FILTER_ASSOC_RESPONSE 0x0002#define RX_FILTER_REASSOC_RESPONSE 0x0008#define RX_FILTER_PROBE_RESPONSE 0x0020#define RX_FILTER_BEACON 0x0100#define RX_FILTER_DISASSOC 0x0400#define RX_FILTER_AUTH 0x0800#define AP_RX_FILTER 0x0400feff#define STA_RX_FILTER 0x0000ffff/* Monitor mode sets filter to 0xfffff */#define CR_ACK_TIMEOUT_EXT CTL_REG(0x0690)#define CR_BCN_FIFO_SEMAPHORE CTL_REG(0x0694)#define CR_IFS_VALUE CTL_REG(0x0698)#define CR_RX_TIME_OUT CTL_REG(0x069C)#define CR_TOTAL_RX_FRM CTL_REG(0x06A0)#define CR_CRC32_CNT CTL_REG(0x06A4)#define CR_CRC16_CNT CTL_REG(0x06A8)#define CR_DECRYPTION_ERR_UNI CTL_REG(0x06AC)#define CR_RX_FIFO_OVERRUN CTL_REG(0x06B0)#define CR_DECRYPTION_ERR_MUL CTL_REG(0x06BC)#define CR_NAV_CNT CTL_REG(0x06C4)#define CR_NAV_CCA CTL_REG(0x06C8)#define CR_RETRY_CNT CTL_REG(0x06CC)#define CR_READ_TCB_ADDR CTL_REG(0x06E8)#define CR_READ_RFD_ADDR CTL_REG(0x06EC)#define CR_CWMIN_CWMAX CTL_REG(0x06F0)#define CR_TOTAL_TX_FRM CTL_REG(0x06F4)/* CAM: Continuous Access Mode (power management) */#define CR_CAM_MODE CTL_REG(0x0700)#define CR_CAM_ROLL_TB_LOW CTL_REG(0x0704)#define CR_CAM_ROLL_TB_HIGH CTL_REG(0x0708)#define CR_CAM_ADDRESS CTL_REG(0x070C)#define CR_CAM_DATA CTL_REG(0x0710)#define CR_ROMDIR CTL_REG(0x0714)#define CR_DECRY_ERR_FLG_LOW CTL_REG(0x0714)#define CR_DECRY_ERR_FLG_HIGH CTL_REG(0x0718)#define CR_WEPKEY0 CTL_REG(0x0720)#define CR_WEPKEY1 CTL_REG(0x0724)#define CR_WEPKEY2 CTL_REG(0x0728)#define CR_WEPKEY3 CTL_REG(0x072C)#define CR_WEPKEY4 CTL_REG(0x0730)#define CR_WEPKEY5 CTL_REG(0x0734)#define CR_WEPKEY6 CTL_REG(0x0738)#define CR_WEPKEY7 CTL_REG(0x073C)#define CR_WEPKEY8 CTL_REG(0x0740)#define CR_WEPKEY9 CTL_REG(0x0744)#define CR_WEPKEY10 CTL_REG(0x0748)#define CR_WEPKEY11 CTL_REG(0x074C)#define CR_WEPKEY12 CTL_REG(0x0750)#define CR_WEPKEY13 CTL_REG(0x0754)#define CR_WEPKEY14 CTL_REG(0x0758)#define CR_WEPKEY15 CTL_REG(0x075c)#define CR_TKIP_MODE CTL_REG(0x0760)#define CR_EEPROM_PROTECT0 CTL_REG(0x0758)#define CR_EEPROM_PROTECT1 CTL_REG(0x075C)#define CR_DBG_FIFO_RD CTL_REG(0x0800)#define CR_DBG_SELECT CTL_REG(0x0804)#define CR_FIFO_Length CTL_REG(0x0808)#define CR_RSSI_MGC CTL_REG(0x0810)#define CR_PON CTL_REG(0x0818)#define CR_RX_ON CTL_REG(0x081C)#define CR_TX_ON CTL_REG(0x0820)#define CR_CHIP_EN CTL_REG(0x0824)#define CR_LO_SW CTL_REG(0x0828)#define CR_TXRX_SW CTL_REG(0x082C)#define CR_S_MD CTL_REG(0x0830)#define CR_USB_DEBUG_PORT CTL_REG(0x0888)#define CR_ZD1211B_TX_PWR_CTL1 CTL_REG(0x0b00)#define CR_ZD1211B_TX_PWR_CTL2 CTL_REG(0x0b04)#define CR_ZD1211B_TX_PWR_CTL3 CTL_REG(0x0b08)#define CR_ZD1211B_TX_PWR_CTL4 CTL_REG(0x0b0c)#define CR_ZD1211B_AIFS_CTL1 CTL_REG(0x0b10)#define CR_ZD1211B_AIFS_CTL2 CTL_REG(0x0b14)#define CR_ZD1211B_TXOP CTL_REG(0x0b20)#define CR_ZD1211B_RETRY_MAX CTL_REG(0x0b28)#define CWIN_SIZE 0x007f043f#define HWINT_ENABLED 0x004f0000#define HWINT_DISABLED 0#define E2P_PWR_INT_GUARD 8#define E2P_CHANNEL_COUNT 14/* If you compare this addresses with the ZYDAS orignal driver, please notify * that we use word mapping for the EEPROM. *//* * Upper 16 bit contains the regulatory domain. */#define E2P_SUBID E2P_REG(0x00)#define E2P_POD E2P_REG(0x02)#define E2P_MAC_ADDR_P1 E2P_REG(0x04)#define E2P_MAC_ADDR_P2 E2P_REG(0x06)#define E2P_PWR_CAL_VALUE1 E2P_REG(0x08)#define E2P_PWR_CAL_VALUE2 E2P_REG(0x0a)#define E2P_PWR_CAL_VALUE3 E2P_REG(0x0c)#define E2P_PWR_CAL_VALUE4 E2P_REG(0x0e)#define E2P_PWR_INT_VALUE1 E2P_REG(0x10)#define E2P_PWR_INT_VALUE2 E2P_REG(0x12)#define E2P_PWR_INT_VALUE3 E2P_REG(0x14)#define E2P_PWR_INT_VALUE4 E2P_REG(0x16)/* Contains a bit for each allowed channel. It gives for Europe (ETSI 0x30) * also only 11 channels. */#define E2P_ALLOWED_CHANNEL E2P_REG(0x18)#define E2P_PHY_REG E2P_REG(0x1a)#define E2P_DEVICE_VER E2P_REG(0x20)#define E2P_36M_CAL_VALUE1 E2P_REG(0x28)#define E2P_36M_CAL_VALUE2 E2P_REG(0x2a)#define E2P_36M_CAL_VALUE3 E2P_REG(0x2c)#define E2P_36M_CAL_VALUE4 E2P_REG(0x2e)#define E2P_11A_INT_VALUE1 E2P_REG(0x30)#define E2P_11A_INT_VALUE2 E2P_REG(0x32)#define E2P_11A_INT_VALUE3 E2P_REG(0x34)#define E2P_11A_INT_VALUE4 E2P_REG(0x36)#define E2P_48M_CAL_VALUE1 E2P_REG(0x38)#define E2P_48M_CAL_VALUE2 E2P_REG(0x3a)#define E2P_48M_CAL_VALUE3 E2P_REG(0x3c)#define E2P_48M_CAL_VALUE4 E2P_REG(0x3e)#define E2P_48M_INT_VALUE1 E2P_REG(0x40)#define E2P_48M_INT_VALUE2 E2P_REG(0x42)#define E2P_48M_INT_VALUE3 E2P_REG(0x44)#define E2P_48M_INT_VALUE4 E2P_REG(0x46)#define E2P_54M_CAL_VALUE1 E2P_REG(0x48) /* ??? */#define E2P_54M_CAL_VALUE2 E2P_REG(0x4a)#define E2P_54M_CAL_VALUE3 E2P_REG(0x4c)#define E2P_54M_CAL_VALUE4 E2P_REG(0x4e)#define E2P_54M_INT_VALUE1 E2P_REG(0x50)#define E2P_54M_INT_VALUE2 E2P_REG(0x52)#define E2P_54M_INT_VALUE3 E2P_REG(0x54)#define E2P_54M_INT_VALUE4 E2P_REG(0x56)/* All 16 bit values */#define FW_FIRMWARE_VER FW_REG(0)/* non-zero if USB high speed connection */#define FW_USB_SPEED FW_REG(1)#define FW_FIX_TX_RATE FW_REG(2)/* Seems to be able to control LEDs over the firmware */#define FW_LINK_STATUS FW_REG(3)#define FW_SOFT_RESET FW_REG(4)#define FW_FLASH_CHK FW_REG(5)enum { CR_BASE_OFFSET = 0x9000, FW_START_OFFSET = 0xee00, FW_BASE_ADDR_OFFSET = FW_START_OFFSET + 0x1d, EEPROM_START_OFFSET = 0xf800, EEPROM_SIZE = 0x800, /* words */ LOAD_CODE_SIZE = 0xe, /* words */ LOAD_VECT_SIZE = 0x10000 - 0xfff7, /* words */ EEPROM_REGS_OFFSET = LOAD_CODE_SIZE + LOAD_VECT_SIZE, E2P_BASE_OFFSET = EEPROM_START_OFFSET + EEPROM_REGS_OFFSET,};#define FW_REG_TABLE_ADDR USB_ADDR(FW_START_OFFSET + 0x1d)enum { /* indices for ofdm_cal_values */ OFDM_36M_INDEX = 0, OFDM_48M_INDEX = 1, OFDM_54M_INDEX = 2,};struct zd_chip { struct zd_usb usb; struct zd_rf rf; struct mutex mutex; u8 e2p_mac[ETH_ALEN]; /* EepSetPoint in the vendor driver */ u8 pwr_cal_values[E2P_CHANNEL_COUNT]; /* integration values in the vendor driver */ u8 pwr_int_values[E2P_CHANNEL_COUNT]; /* SetPointOFDM in the vendor driver */ u8 ofdm_cal_values[3][E2P_CHANNEL_COUNT]; u8 pa_type:4, patch_cck_gain:1, patch_cr157:1, patch_6m_band_edge:1, is_zd1211b:1;};static inline struct zd_chip *zd_usb_to_chip(struct zd_usb *usb){ return container_of(usb, struct zd_chip, usb);}static inline struct zd_chip *zd_rf_to_chip(struct zd_rf *rf){ return container_of(rf, struct zd_chip, rf);}#define zd_chip_dev(chip) (&(chip)->usb.intf->dev)void zd_chip_init(struct zd_chip *chip, struct net_device *netdev, struct usb_interface *intf);void zd_chip_clear(struct zd_chip *chip);int zd_chip_init_hw(struct zd_chip *chip, u8 device_type);int zd_chip_reset(struct zd_chip *chip);static inline int zd_ioread16v_locked(struct zd_chip *chip, u16 *values, const zd_addr_t *addresses, unsigned int count){ ZD_ASSERT(mutex_is_locked(&chip->mutex)); return zd_usb_ioread16v(&chip->usb, values, addresses, count);}static inline int zd_ioread16_locked(struct zd_chip *chip, u16 *value, const zd_addr_t addr){ ZD_ASSERT(mutex_is_locked(&chip->mutex)); return zd_usb_ioread16(&chip->usb, value, addr);}int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addresses, unsigned int count);static inline int zd_ioread32_locked(struct zd_chip *chip, u32 *value, const zd_addr_t addr){ return zd_ioread32v_locked(chip, value, (const zd_addr_t *)&addr, 1);}static inline int zd_iowrite16_locked(struct zd_chip *chip, u16 value, zd_addr_t addr){ struct zd_ioreq16 ioreq; ZD_ASSERT(mutex_is_locked(&chip->mutex)); ioreq.addr = addr; ioreq.value = value; return zd_usb_iowrite16v(&chip->usb, &ioreq, 1);}int zd_iowrite16a_locked(struct zd_chip *chip, const struct zd_ioreq16 *ioreqs, unsigned int count);int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, unsigned int count);static inline int zd_iowrite32_locked(struct zd_chip *chip, u32 value, zd_addr_t addr){ struct zd_ioreq32 ioreq; ioreq.addr = addr; ioreq.value = value; return _zd_iowrite32v_locked(chip, &ioreq, 1);}int zd_iowrite32a_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, unsigned int count);static inline int zd_rfwrite_locked(struct zd_chip *chip, u32 value, u8 bits){ ZD_ASSERT(mutex_is_locked(&chip->mutex)); return zd_usb_rfwrite(&chip->usb, value, bits);}int zd_rfwritev_locked(struct zd_chip *chip, const u32* values, unsigned int count, u8 bits);/* Locking functions for reading and writing registers. * The different parameters are intentional. */int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value);int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value);int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value);int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value);int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, u32 *values, unsigned int count);int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, unsigned int count);int zd_chip_set_channel(struct zd_chip *chip, u8 channel);static inline u8 _zd_chip_get_channel(struct zd_chip *chip){ return chip->rf.channel;}u8 zd_chip_get_channel(struct zd_chip *chip);int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain);void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr);int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr);int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr);int zd_chip_switch_radio_on(struct zd_chip *chip);int zd_chip_switch_radio_off(struct zd_chip *chip);int zd_chip_enable_int(struct zd_chip *chip);void zd_chip_disable_int(struct zd_chip *chip);int zd_chip_enable_rx(struct zd_chip *chip);void zd_chip_disable_rx(struct zd_chip *chip);int zd_chip_enable_hwint(struct zd_chip *chip);int zd_chip_disable_hwint(struct zd_chip *chip);static inline int zd_get_encryption_type(struct zd_chip *chip, u32 *type){ return zd_ioread32(chip, CR_ENCRYPTION_TYPE, type);}static inline int zd_set_encryption_type(struct zd_chip *chip, u32 type){ return zd_iowrite32(chip, CR_ENCRYPTION_TYPE, type);}static inline int zd_chip_get_basic_rates(struct zd_chip *chip, u16 *cr_rates){ return zd_ioread16(chip, CR_BASIC_RATE_TBL, cr_rates);}int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates);static inline int zd_chip_set_rx_filter(struct zd_chip *chip, u32 filter){ return zd_iowrite32(chip, CR_RX_FILTER, filter);}int zd_chip_lock_phy_regs(struct zd_chip *chip);int zd_chip_unlock_phy_regs(struct zd_chip *chip);enum led_status { LED_OFF = 0, LED_ON = 1, LED_FLIP = 2, LED_STATUS = 3,};int zd_chip_led_status(struct zd_chip *chip, int led, enum led_status status);int zd_chip_led_flip(struct zd_chip *chip, int led, const unsigned int *phases_msecs, unsigned int count);int zd_set_beacon_interval(struct zd_chip *chip, u32 interval);static inline int zd_get_beacon_interval(struct zd_chip *chip, u32 *interval){ return zd_ioread32(chip, CR_BCN_INTERVAL, interval);}struct rx_status;u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size, const struct rx_status *status);u8 zd_rx_strength_percent(u8 rssi);u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status);#endif /* _ZD_CHIP_H */⌨️ 快捷键说明
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