📄 zd_chip.h
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/* zd_chip.h * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */#ifndef _ZD_CHIP_H#define _ZD_CHIP_H#include "zd_types.h"#include "zd_rf.h"#include "zd_usb.h"/* Header for the Media Access Controller (MAC) and the Baseband Processor * (BBP). It appears that the ZD1211 wraps the old ZD1205 with USB glue and * adds a processor for handling the USB protocol. *//* 8-bit hardware registers */#define CR0 CTL_REG(0x0000)#define CR1 CTL_REG(0x0004)#define CR2 CTL_REG(0x0008)#define CR3 CTL_REG(0x000C)#define CR5 CTL_REG(0x0010)/* bit 5: if set short preamble used * bit 6: filter band - Japan channel 14 on, else off */#define CR6 CTL_REG(0x0014)#define CR7 CTL_REG(0x0018)#define CR8 CTL_REG(0x001C)#define CR4 CTL_REG(0x0020)#define CR9 CTL_REG(0x0024)/* bit 2: antenna switch (together with CR10) */#define CR10 CTL_REG(0x0028)/* bit 1: antenna switch (together with CR9) * RF2959 controls with CR11 radion on and off */#define CR11 CTL_REG(0x002C)/* bit 6: TX power control for OFDM * RF2959 controls with CR10 radio on and off */#define CR12 CTL_REG(0x0030)#define CR13 CTL_REG(0x0034)#define CR14 CTL_REG(0x0038)#define CR15 CTL_REG(0x003C)#define CR16 CTL_REG(0x0040)#define CR17 CTL_REG(0x0044)#define CR18 CTL_REG(0x0048)#define CR19 CTL_REG(0x004C)#define CR20 CTL_REG(0x0050)#define CR21 CTL_REG(0x0054)#define CR22 CTL_REG(0x0058)#define CR23 CTL_REG(0x005C)#define CR24 CTL_REG(0x0060) /* CCA threshold */#define CR25 CTL_REG(0x0064)#define CR26 CTL_REG(0x0068)#define CR27 CTL_REG(0x006C)#define CR28 CTL_REG(0x0070)#define CR29 CTL_REG(0x0074)#define CR30 CTL_REG(0x0078)#define CR31 CTL_REG(0x007C) /* TX power control for RF in CCK mode */#define CR32 CTL_REG(0x0080)#define CR33 CTL_REG(0x0084)#define CR34 CTL_REG(0x0088)#define CR35 CTL_REG(0x008C)#define CR36 CTL_REG(0x0090)#define CR37 CTL_REG(0x0094)#define CR38 CTL_REG(0x0098)#define CR39 CTL_REG(0x009C)#define CR40 CTL_REG(0x00A0)#define CR41 CTL_REG(0x00A4)#define CR42 CTL_REG(0x00A8)#define CR43 CTL_REG(0x00AC)#define CR44 CTL_REG(0x00B0)#define CR45 CTL_REG(0x00B4)#define CR46 CTL_REG(0x00B8)#define CR47 CTL_REG(0x00BC) /* CCK baseband gain * (patch value might be in EEPROM) */#define CR48 CTL_REG(0x00C0)#define CR49 CTL_REG(0x00C4)#define CR50 CTL_REG(0x00C8)#define CR51 CTL_REG(0x00CC) /* TX power control for RF in 6-36M modes */#define CR52 CTL_REG(0x00D0) /* TX power control for RF in 48M mode */#define CR53 CTL_REG(0x00D4) /* TX power control for RF in 54M mode */#define CR54 CTL_REG(0x00D8)#define CR55 CTL_REG(0x00DC)#define CR56 CTL_REG(0x00E0)#define CR57 CTL_REG(0x00E4)#define CR58 CTL_REG(0x00E8)#define CR59 CTL_REG(0x00EC)#define CR60 CTL_REG(0x00F0)#define CR61 CTL_REG(0x00F4)#define CR62 CTL_REG(0x00F8)#define CR63 CTL_REG(0x00FC)#define CR64 CTL_REG(0x0100)#define CR65 CTL_REG(0x0104) /* OFDM 54M calibration */#define CR66 CTL_REG(0x0108) /* OFDM 48M calibration */#define CR67 CTL_REG(0x010C) /* OFDM 36M calibration */#define CR68 CTL_REG(0x0110) /* CCK calibration */#define CR69 CTL_REG(0x0114)#define CR70 CTL_REG(0x0118)#define CR71 CTL_REG(0x011C)#define CR72 CTL_REG(0x0120)#define CR73 CTL_REG(0x0124)#define CR74 CTL_REG(0x0128)#define CR75 CTL_REG(0x012C)#define CR76 CTL_REG(0x0130)#define CR77 CTL_REG(0x0134)#define CR78 CTL_REG(0x0138)#define CR79 CTL_REG(0x013C)#define CR80 CTL_REG(0x0140)#define CR81 CTL_REG(0x0144)#define CR82 CTL_REG(0x0148)#define CR83 CTL_REG(0x014C)#define CR84 CTL_REG(0x0150)#define CR85 CTL_REG(0x0154)#define CR86 CTL_REG(0x0158)#define CR87 CTL_REG(0x015C)#define CR88 CTL_REG(0x0160)#define CR89 CTL_REG(0x0164)#define CR90 CTL_REG(0x0168)#define CR91 CTL_REG(0x016C)#define CR92 CTL_REG(0x0170)#define CR93 CTL_REG(0x0174)#define CR94 CTL_REG(0x0178)#define CR95 CTL_REG(0x017C)#define CR96 CTL_REG(0x0180)#define CR97 CTL_REG(0x0184)#define CR98 CTL_REG(0x0188)#define CR99 CTL_REG(0x018C)#define CR100 CTL_REG(0x0190)#define CR101 CTL_REG(0x0194)#define CR102 CTL_REG(0x0198)#define CR103 CTL_REG(0x019C)#define CR104 CTL_REG(0x01A0)#define CR105 CTL_REG(0x01A4)#define CR106 CTL_REG(0x01A8)#define CR107 CTL_REG(0x01AC)#define CR108 CTL_REG(0x01B0)#define CR109 CTL_REG(0x01B4)#define CR110 CTL_REG(0x01B8)#define CR111 CTL_REG(0x01BC)#define CR112 CTL_REG(0x01C0)#define CR113 CTL_REG(0x01C4)#define CR114 CTL_REG(0x01C8)#define CR115 CTL_REG(0x01CC)#define CR116 CTL_REG(0x01D0)#define CR117 CTL_REG(0x01D4)#define CR118 CTL_REG(0x01D8)#define CR119 CTL_REG(0x01DC)#define CR120 CTL_REG(0x01E0)#define CR121 CTL_REG(0x01E4)#define CR122 CTL_REG(0x01E8)#define CR123 CTL_REG(0x01EC)#define CR124 CTL_REG(0x01F0)#define CR125 CTL_REG(0x01F4)#define CR126 CTL_REG(0x01F8)#define CR127 CTL_REG(0x01FC)#define CR128 CTL_REG(0x0200)#define CR129 CTL_REG(0x0204)#define CR130 CTL_REG(0x0208)#define CR131 CTL_REG(0x020C)#define CR132 CTL_REG(0x0210)#define CR133 CTL_REG(0x0214)#define CR134 CTL_REG(0x0218)#define CR135 CTL_REG(0x021C)#define CR136 CTL_REG(0x0220)#define CR137 CTL_REG(0x0224)#define CR138 CTL_REG(0x0228)#define CR139 CTL_REG(0x022C)#define CR140 CTL_REG(0x0230)#define CR141 CTL_REG(0x0234)#define CR142 CTL_REG(0x0238)#define CR143 CTL_REG(0x023C)#define CR144 CTL_REG(0x0240)#define CR145 CTL_REG(0x0244)#define CR146 CTL_REG(0x0248)#define CR147 CTL_REG(0x024C)#define CR148 CTL_REG(0x0250)#define CR149 CTL_REG(0x0254)#define CR150 CTL_REG(0x0258)#define CR151 CTL_REG(0x025C)#define CR152 CTL_REG(0x0260)#define CR153 CTL_REG(0x0264)#define CR154 CTL_REG(0x0268)#define CR155 CTL_REG(0x026C)#define CR156 CTL_REG(0x0270)#define CR157 CTL_REG(0x0274)#define CR158 CTL_REG(0x0278)#define CR159 CTL_REG(0x027C)#define CR160 CTL_REG(0x0280)#define CR161 CTL_REG(0x0284)#define CR162 CTL_REG(0x0288)#define CR163 CTL_REG(0x028C)#define CR164 CTL_REG(0x0290)#define CR165 CTL_REG(0x0294)#define CR166 CTL_REG(0x0298)#define CR167 CTL_REG(0x029C)#define CR168 CTL_REG(0x02A0)#define CR169 CTL_REG(0x02A4)#define CR170 CTL_REG(0x02A8)#define CR171 CTL_REG(0x02AC)#define CR172 CTL_REG(0x02B0)#define CR173 CTL_REG(0x02B4)#define CR174 CTL_REG(0x02B8)#define CR175 CTL_REG(0x02BC)#define CR176 CTL_REG(0x02C0)#define CR177 CTL_REG(0x02C4)#define CR178 CTL_REG(0x02C8)#define CR179 CTL_REG(0x02CC)#define CR180 CTL_REG(0x02D0)#define CR181 CTL_REG(0x02D4)#define CR182 CTL_REG(0x02D8)#define CR183 CTL_REG(0x02DC)#define CR184 CTL_REG(0x02E0)#define CR185 CTL_REG(0x02E4)#define CR186 CTL_REG(0x02E8)#define CR187 CTL_REG(0x02EC)#define CR188 CTL_REG(0x02F0)#define CR189 CTL_REG(0x02F4)#define CR190 CTL_REG(0x02F8)#define CR191 CTL_REG(0x02FC)#define CR192 CTL_REG(0x0300)#define CR193 CTL_REG(0x0304)#define CR194 CTL_REG(0x0308)#define CR195 CTL_REG(0x030C)#define CR196 CTL_REG(0x0310)#define CR197 CTL_REG(0x0314)#define CR198 CTL_REG(0x0318)#define CR199 CTL_REG(0x031C)#define CR200 CTL_REG(0x0320)#define CR201 CTL_REG(0x0324)#define CR202 CTL_REG(0x0328)#define CR203 CTL_REG(0x032C) /* I2C bus template value & flash control */#define CR204 CTL_REG(0x0330)#define CR205 CTL_REG(0x0334)#define CR206 CTL_REG(0x0338)#define CR207 CTL_REG(0x033C)#define CR208 CTL_REG(0x0340)#define CR209 CTL_REG(0x0344)#define CR210 CTL_REG(0x0348)#define CR211 CTL_REG(0x034C)#define CR212 CTL_REG(0x0350)#define CR213 CTL_REG(0x0354)#define CR214 CTL_REG(0x0358)#define CR215 CTL_REG(0x035C)#define CR216 CTL_REG(0x0360)#define CR217 CTL_REG(0x0364)#define CR218 CTL_REG(0x0368)#define CR219 CTL_REG(0x036C)#define CR220 CTL_REG(0x0370)#define CR221 CTL_REG(0x0374)#define CR222 CTL_REG(0x0378)#define CR223 CTL_REG(0x037C)#define CR224 CTL_REG(0x0380)#define CR225 CTL_REG(0x0384)#define CR226 CTL_REG(0x0388)#define CR227 CTL_REG(0x038C)#define CR228 CTL_REG(0x0390)#define CR229 CTL_REG(0x0394)#define CR230 CTL_REG(0x0398)#define CR231 CTL_REG(0x039C)#define CR232 CTL_REG(0x03A0)#define CR233 CTL_REG(0x03A4)#define CR234 CTL_REG(0x03A8)#define CR235 CTL_REG(0x03AC)#define CR236 CTL_REG(0x03B0)#define CR240 CTL_REG(0x03C0)/* bit 7: host-controlled RF register writes * CR241-CR245: for hardware controlled writing of RF bits, not needed for * USB */#define CR241 CTL_REG(0x03C4)#define CR242 CTL_REG(0x03C8)#define CR243 CTL_REG(0x03CC)#define CR244 CTL_REG(0x03D0)#define CR245 CTL_REG(0x03D4)#define CR251 CTL_REG(0x03EC) /* only used for activation and deactivation of * Airoha RFs AL2230 and AL7230B */#define CR252 CTL_REG(0x03F0)#define CR253 CTL_REG(0x03F4)#define CR254 CTL_REG(0x03F8)#define CR255 CTL_REG(0x03FC)#define CR_MAX_PHY_REG 255/* Taken from the ZYDAS driver, not all of them are relevant for the ZSD1211 * driver. */#define CR_RF_IF_CLK CTL_REG(0x0400)#define CR_RF_IF_DATA CTL_REG(0x0404)#define CR_PE1_PE2 CTL_REG(0x0408)#define CR_PE2_DLY CTL_REG(0x040C)#define CR_LE1 CTL_REG(0x0410)#define CR_LE2 CTL_REG(0x0414)/* Seems to enable/disable GPI (General Purpose IO?) */#define CR_GPI_EN CTL_REG(0x0418)#define CR_RADIO_PD CTL_REG(0x042C)#define CR_RF2948_PD CTL_REG(0x042C)#define CR_ENABLE_PS_MANUAL_AGC CTL_REG(0x043C)#define CR_CONFIG_PHILIPS CTL_REG(0x0440)#define CR_SA2400_SER_AP CTL_REG(0x0444)#define CR_I2C_WRITE CTL_REG(0x0444)#define CR_SA2400_SER_RP CTL_REG(0x0448)#define CR_RADIO_PE CTL_REG(0x0458)#define CR_RST_BUS_MASTER CTL_REG(0x045C)#define CR_RFCFG CTL_REG(0x0464)#define CR_HSTSCHG CTL_REG(0x046C)#define CR_PHY_ON CTL_REG(0x0474)#define CR_RX_DELAY CTL_REG(0x0478)#define CR_RX_PE_DELAY CTL_REG(0x047C)#define CR_GPIO_1 CTL_REG(0x0490)#define CR_GPIO_2 CTL_REG(0x0494)#define CR_EncryBufMux CTL_REG(0x04A8)#define CR_PS_CTRL CTL_REG(0x0500)#define CR_ADDA_PWR_DWN CTL_REG(0x0504)#define CR_ADDA_MBIAS_WARMTIME CTL_REG(0x0508)#define CR_MAC_PS_STATE CTL_REG(0x050C)#define CR_INTERRUPT CTL_REG(0x0510)#define INT_TX_COMPLETE 0x00000001#define INT_RX_COMPLETE 0x00000002#define INT_RETRY_FAIL 0x00000004#define INT_WAKEUP 0x00000008#define INT_DTIM_NOTIFY 0x00000020#define INT_CFG_NEXT_BCN 0x00000040#define INT_BUS_ABORT 0x00000080#define INT_TX_FIFO_READY 0x00000100#define INT_UART 0x00000200#define INT_TX_COMPLETE_EN 0x00010000#define INT_RX_COMPLETE_EN 0x00020000#define INT_RETRY_FAIL_EN 0x00040000#define INT_WAKEUP_EN 0x00080000#define INT_DTIM_NOTIFY_EN 0x00200000#define INT_CFG_NEXT_BCN_EN 0x00400000#define INT_BUS_ABORT_EN 0x00800000#define INT_TX_FIFO_READY_EN 0x01000000#define INT_UART_EN 0x02000000#define CR_TSF_LOW_PART CTL_REG(0x0514)#define CR_TSF_HIGH_PART CTL_REG(0x0518)/* Following three values are in time units (1024us) * Following condition must be met: * atim < tbtt < bcn */#define CR_ATIM_WND_PERIOD CTL_REG(0x051C)#define CR_BCN_INTERVAL CTL_REG(0x0520)#define CR_PRE_TBTT CTL_REG(0x0524)/* in units of TU(1024us) *//* for UART support */#define CR_UART_RBR_THR_DLL CTL_REG(0x0540)#define CR_UART_DLM_IER CTL_REG(0x0544)#define CR_UART_IIR_FCR CTL_REG(0x0548)#define CR_UART_LCR CTL_REG(0x054c)#define CR_UART_MCR CTL_REG(0x0550)#define CR_UART_LSR CTL_REG(0x0554)#define CR_UART_MSR CTL_REG(0x0558)#define CR_UART_ECR CTL_REG(0x055c)#define CR_UART_STATUS CTL_REG(0x0560)#define CR_PCI_TX_ADDR_P1 CTL_REG(0x0600)#define CR_PCI_TX_AddR_P2 CTL_REG(0x0604)#define CR_PCI_RX_AddR_P1 CTL_REG(0x0608)#define CR_PCI_RX_AddR_P2 CTL_REG(0x060C)/* must be overwritten if custom MAC address will be used */#define CR_MAC_ADDR_P1 CTL_REG(0x0610)#define CR_MAC_ADDR_P2 CTL_REG(0x0614)#define CR_BSSID_P1 CTL_REG(0x0618)#define CR_BSSID_P2 CTL_REG(0x061C)#define CR_BCN_PLCP_CFG CTL_REG(0x0620)#define CR_GROUP_HASH_P1 CTL_REG(0x0624)#define CR_GROUP_HASH_P2 CTL_REG(0x0628)#define CR_RX_TIMEOUT CTL_REG(0x062C)/* Basic rates supported by the BSS. When producing ACK or CTS messages, the * device will use a rate in this table that is less than or equal to the rate * of the incoming frame which prompted the response */#define CR_BASIC_RATE_TBL CTL_REG(0x0630)#define CR_RATE_1M 0x0001 /* 802.11b */#define CR_RATE_2M 0x0002 /* 802.11b */#define CR_RATE_5_5M 0x0004 /* 802.11b */#define CR_RATE_11M 0x0008 /* 802.11b */#define CR_RATE_6M 0x0100 /* 802.11g */#define CR_RATE_9M 0x0200 /* 802.11g */#define CR_RATE_12M 0x0400 /* 802.11g */#define CR_RATE_18M 0x0800 /* 802.11g */#define CR_RATE_24M 0x1000 /* 802.11g */#define CR_RATE_36M 0x2000 /* 802.11g */#define CR_RATE_48M 0x4000 /* 802.11g */#define CR_RATE_54M 0x8000 /* 802.11g */#define CR_RATES_80211G 0xff00#define CR_RATES_80211B 0x000f⌨️ 快捷键说明
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